base_fw.h

Go to the documentation of this file.

/* SPDX-License-Identifier: BSD-3-Clause
 *
 * Copyright(c) 2021 Intel Corporation. All rights reserved.
 */
 
/*
 * Some of the structures may contain programming implementations that makes them
 * unsuitable for generic use and general usage.
 */
 
#ifndef __SOF_IPC4_BASE_FW_H__
#define __SOF_IPC4_BASE_FW_H__
 
#define IPC4_MAX_CLK_STATES 0
 
#define IPC4_MAX_SRC_QUEUE 8
 
#define IPC4_MAX_DST_QUEUE 8
 
#define IPC4_MAX_MODULE_INSTANCES 256
 
#define IPC4_MAX_LL_TASKS_PER_PRI_COUNT 16
 
#define IPC4_MAX_DP_TASKS_COUNT 16
 
#define IPC4_MAX_LIBS_COUNT 16
 
#define IPC4_MAX_PPL_COUNT 32
 
enum ipc4_basefw_params {
    IPC4_DSP_PROPERTIES = 0,
 
    IPC4_DSP_RESOURCE_STATE = 1,
 
    IPC4_RESERVED = 2,
 
    IPC4_NOTIFICATION_MASK = 3,
 
    IPC4_ASTATE_TABLE = 4,
 
    IPC4_DMA_CONTROL = 5,
 
    IPC4_ENABLE_LOGS = 6,
 
    IPC4_FW_CONFIG = 7,
 
    IPC4_HW_CONFIG_GET = 8,
 
    IPC4_MODULES_INFO_GET = 9,
 
    IPC4_PIPELINE_LIST_INFO_GET = 10,
 
    IPC4_PIPELINE_PROPS_GET = 11,
 
    IPC4_SCHEDULERS_INFO_GET = 12,
 
    IPC4_GATEWAYS_INFO_GET = 13,
 
    IPC4_MEMORY_STATE_INFO_GET = 14,
 
    IPC4_POWER_STATE_INFO_GET = 15,
 
    IPC4_LIBRARIES_INFO_GET = 16,
 
    IPC4_PERF_MEASUREMENTS_STATE = 17,
 
    IPC4_GLOBAL_PERF_DATA = 18,
 
    IPC4_L2_CACHE_INFO_GET = 19,
 
    IPC4_SYSTEM_TIME = 20,
 
    IPC4_PERFORMANCE_CONFIGURATION = 21,
 
    IPC4_REGISTER_KCPS = 22,
 
    IPC4_RESOURCE_ALLOCATION_REQUEST = 23,
 
    IPC4_IO_PERF_MEASUREMENTS_STATE  = 24,
 
    IPC4_IO_GLOBAL_PERF_DATA         = 25,
 
    IPC4_GET_MODULE_ID               = 26,
 
    IPC4_EXTENDED_SYSTEM_TIME        = 27,
 
    IPC4_TELEMETRY_STATE             = 28,
 
    IPC4_TELEMETRY_DATA              = 29,
 
    IPC4_EXTENDED_GLOBAL_PERF_DATA   = 30,
 
    IPC4_SDW_OWNERSHIP               = 31,
 
    IPC4_MIC_PRIVACY_HW_MANAGED_STATE_CHANGE = 35,
 
    IPC4_SET_MIC_PRIVACY_FW_MANAGED_POLICY_MASK = 36,
};
 
enum ipc4_fw_config_params {
    IPC4_FW_VERSION_FW_CFG                  = 0,
    IPC4_MEMORY_RECLAIMED_FW_CFG            = 1,
    IPC4_SLOW_CLOCK_FREQ_HZ_FW_CFG          = 2,
    IPC4_FAST_CLOCK_FREQ_HZ_FW_CFG          = 3,
    IPC4_DMA_BUFFER_CONFIG_FW_CFG           = 4,
    IPC4_ALH_SUPPORT_LEVEL_FW_CFG           = 5,
    IPC4_DL_MAILBOX_BYTES_FW_CFG            = 6,
    IPC4_UL_MAILBOX_BYTES_FW_CFG            = 7,
    IPC4_TRACE_LOG_BYTES_FW_CFG             = 8,
    IPC4_MAX_PPL_CNT_FW_CFG                 = 9,
    IPC4_MAX_ASTATE_COUNT_FW_CFG            = 10,
    IPC4_MAX_MODULE_PIN_COUNT_FW_CFG        = 11,
    IPC4_MODULES_COUNT_FW_CFG               = 12,
    IPC4_MAX_MOD_INST_COUNT_FW_CFG          = 13,
    IPC4_MAX_LL_TASKS_PER_PRI_COUNT_FW_CFG  = 14,
    IPC4_LL_PRI_COUNT                       = 15,
    IPC4_MAX_DP_TASKS_COUNT_FW_CFG          = 16,
    IPC4_MAX_LIBS_COUNT_FW_CFG              = 17,
    IPC4_SCHEDULER_CONFIGURATION            = 18,
    IPC4_XTAL_FREQ_HZ_FW_CFG                = 19,
    IPC4_CLOCKS_CONFIGURATION               = 20,
    IPC4_UAOL_SUPPORT                       = 21,
    IPC4_POWER_GATING_POLICY                = 22,
    IPC4_ASSERT_MODE                        = 23,
    IPC4_TELEMETRY_BUFFER_SIZE              = 24,
    IPC4_BUS_HARDWARE_ID                    = 25,
    IPC4_DEBUG_WINDOW_SIZE                  = 26,
    IPC4_KPB_RT_SINK_COUNT                  = 27,
    IPC4_DMI_FORCE_L1_EXIT                  = 28,
    IPC4_FW_CONTEXT_SAVE                    = 29,
    IPC4_FW_MIN_HOST_BUFFER_PERIODS         = 33,
    IPC4_FW_SOF_INFO                        = 35,
    IPC4_FW_CFG_PARAMS_COUNT,
    IPC4_MAX_FW_CFG_PARAM = IPC4_FW_CFG_PARAMS_COUNT - 1,
};
 
enum ipc4_fw_sof_info_params {
    IPC4_SOF_CODEC_INFO = 0,
 
    IPC4_SOF_CFG_PARAMS_COUNT,
    IPC4_MAX_SOF_CFG_PARAM = IPC4_SOF_CFG_PARAMS_COUNT - 1,
};
 
enum ipc4_hw_config_params {
    IPC4_CAVS_VER_HW_CFG             = 0,
    IPC4_DSP_CORES_HW_CFG            = 1,
    IPC4_MEM_PAGE_BYTES_HW_CFG       = 2,
    IPC4_TOTAL_PHYS_MEM_PAGES_HW_CFG = 3,
    IPC4_I2S_CAPS_HW_CFG             = 4,
    IPC4_GPDMA_CAPS_HW_CFG           = 5,
    IPC4_GATEWAY_COUNT_HW_CFG        = 6,
    IPC4_HP_EBB_COUNT_HW_CFG         = 7,
    IPC4_LP_EBB_COUNT_HW_CFG         = 8,
    IPC4_EBB_SIZE_BYTES_HW_CFG       = 9,
    IPC4_UAOL_CAPS_HW_CFG            = 10,
    IPC4_INTEL_MIC_PRIVACY_CAPS_HW_CFG = 11
};
 
enum ipc4_memory_type {
    IPC4_HP_SRAM_MEMORY = 0,
    IPC4_LP_SRAM_MEMORY = 1
};
 
enum ipc4_resource_state_request {
    IPC4_FREE_PHYS_MEM_PAGES = 0
};
 
struct ipc4_phys_mem_pages {
    uint32_t mem_type; 
    uint32_t pages;    
} __attribute__((packed, aligned(4)));
 
#define IPC4_UNDERRUN_AT_GATEWAY_NOTIFICATION_MASK_IDX  0
#define IPC4_UNDERRUN_AT_MIXER_NOTIFICATION_MASK_IDX    1
#define IPC4_BUDGET_VIOLATION_NOTIFICATION_MASK_IDX 2
#define IPC4_OVERRUN_AT_GATEWAY_NOTIFICATION_MASK_IDX   3
 
struct ipc4_notification_mask_info {
    uint32_t ntfy_mask;
    uint32_t enabled_mask;
} __attribute__((packed, aligned(4)));
 
enum ipc4_clock_src {
    IPC4_CLOCK_SRC_XTAL = 0,
    IPC4_CLOCK_SRC_LP_RING_OSC,
    IPC4_CLOCK_SRC_HP_RING_OSC,
    IPC4_CLOCK_SRC_WOV_XTAL,
    IPC4_CLOCK_SRC_INVALID,
    IPC4_CLOCK_SRC_MAX_IDX = IPC4_CLOCK_SRC_INVALID - 1,
};
 
struct ipc4_astate {
    uint32_t kcps;
    enum ipc4_clock_src clock_src;
} __attribute__((packed, aligned(4)));
 
struct ipc4_astate_table {
    uint32_t astates_count_;
    struct ipc4_astate astates_[3];
} __attribute__((packed, aligned(4)));
 
struct ipc4_dma_control {
    uint32_t node_id;       
    uint32_t config_length; 
    uint32_t config_data[0]; 
} __attribute__((packed, aligned(4)));
 
enum ipc4_perf_measurements_state_set {
    IPC4_PERF_MEASUREMENTS_DISABLED = 0, 
    IPC4_PERF_MEASUREMENTS_STOPPED = 1,  
    IPC4_PERF_MEASUREMENTS_STARTED = 2,  
    IPC4_PERF_MEASUREMENTS_PAUSED = 3,   
};
 
struct ipc4_perf_data_item {
    uint32_t  resource_id; 
    uint32_t  power_mode : 1; 
    uint32_t  rsvd       : 30; 
    uint32_t  is_removed : 1;  
    uint32_t  peak_kcps;  
    uint32_t  avg_kcps;   
} __attribute__((packed, aligned(4)));
 
struct ipc4_perf_data_item_mi {
    struct ipc4_perf_data_item item; 
    uint32_t total_iteration_count;  
    uint64_t total_cycles_consumed;  
} __attribute__((packed, aligned(4)));
 
struct ipc4_global_perf_data {
    uint32_t perf_item_count; 
    struct ipc4_perf_data_item perf_items[1]; 
} __attribute__((packed, aligned(4)));
 
enum ipc4_low_latency_interrupt_source {
    IPC4_LOW_POWER_TIMER_INTERRUPT_SOURCE = 1, 
    IPC4_DMA_GATEWAY_INTERRUPT_SOURCE = 2      
};
 
struct ipc4_scheduler_config {
    uint32_t sys_tick_multiplier; 
    uint32_t sys_tick_divider;    
    uint32_t sys_tick_source;     
    uint32_t sys_tick_cfg_length; 
    uint32_t sys_tick_cfg[1];     
} __attribute__((packed, aligned(4)));
 
struct ipc4_system_time {
    uint32_t val_l; 
    uint32_t val_u; 
} __attribute__((packed, aligned(4)));
 
struct ipc4_system_time_info {
    struct ipc4_system_time host_time; 
    struct ipc4_system_time dsp_time;  
} __attribute__((packed, aligned(4)));
 
struct ipc4_ext_system_time {
    uint32_t utc_l; 
    uint32_t utc_u; 
    uint32_t rtc_l; 
    uint32_t rtc_u; 
    uint32_t art_l; 
    uint32_t art_u; 
};
 
enum ipc4_pipeline_attributes {
    IPC4_ULTRA_LOW_POWER     = 0,
    IPC4_AUTONOMOUS_RESET     = 1,
};
 
enum ipc4_resource_allocation_type {
    IPC4_RAT_DSP_KCPS   = 0, 
    IPC4_RAT_MEMORY     = 1, 
};
 
struct ipc4_resource_kcps {
    uint32_t core_id; 
    int32_t kcps;     
} __attribute__((packed, aligned(4)));
 
struct ipc4_resource_memory {
    uint32_t address; 
    uint32_t size;    
} __attribute__((packed, aligned(4)));
 
struct ipc4_resource_request {
    uint32_t ra_type; 
    union {
        struct ipc4_resource_kcps kcps;     
        struct ipc4_resource_memory memory; 
    } ra_data; 
} __attribute__((packed, aligned(4)));
 
#define IPC4_LPSRAM_STATE  0
#define IPC4_HPSRAM_STATE  1
 
struct ipc4_sram_state_page_alloc {
    uint32_t page_alloc_count; 
    uint16_t page_alloc[1];
} __attribute__((packed, aligned(4)));
 
struct ipc4_sram_state_info {
    uint32_t free_phys_mem_pages;    
    uint32_t ebb_state_dword_count;  
    uint32_t ebb_state[1];
    struct ipc4_sram_state_page_alloc page_alloc_struct; 
} __attribute__((packed, aligned(4)));
 
enum ipc4_alh_version {
    IPC4_ALH_NO_SUPPORT,        
    IPC4_ALH_CAVS_1_8 = 0x10000, 
};
 
struct ipc4_library_props {
    uint32_t id;             
    uint8_t name[8];         
    uint16_t major_version;  
    uint16_t minor_version;  
    uint16_t hotfix_version; 
    uint16_t build_version;  
    uint32_t num_module_entries; 
} __packed __aligned(4);
 
struct ipc4_libraries_info {
    uint32_t library_count; 
    struct ipc4_library_props libraries[0]; 
} __packed __aligned(4);
 
struct ipc4_log_state_info {
    uint32_t  aging_timer_period;
    uint32_t  fifo_full_timer_period;
    uint32_t  enable;
    uint32_t logs_mask[IPC4_MAX_LIBS_COUNT];
} __attribute__((packed, aligned(4)));
 
enum ipc4_power_state_type {
    IPC4_ACTIVE_CORES_MASK = 0, 
    IPC4_CORE_KCPS = 1,         
};
 
struct task_props {
    uint32_t  task_id; 
    uint32_t  module_instance_count; 
    uint32_t  module_instance_id[];  
} __packed __aligned(4);
 
struct scheduler_props {
    uint32_t   processing_domain; 
    uint32_t   core_id;           
    uint32_t   task_count;        
    struct task_props task_info[]; 
} __packed __aligned(4);
 
struct schedulers_info {
    uint32_t scheduler_count; 
    struct scheduler_props scheduler_info[]; 
} __packed __aligned(4);
 
struct ipc4_system_time_info *basefw_get_system_time_info(void);
 
static const uint32_t I2S_VER_30_PTL       = 0x40000;
 
struct perf_data_item {
    uint32_t resource_id; 
    uint32_t power_mode : 1; 
    uint32_t rsvd : 30;      
    uint32_t is_removed : 1; 
    uint32_t peak_kcps;      
    uint32_t avg_kcps;       
} __packed __aligned(4);
 
struct ext_perf_data_item {
    uint32_t resource_id; 
    uint32_t power_mode : 1; 
    uint32_t rsvd : 30;      
    uint32_t is_removed : 1; 
    uint32_t module_peak_dsp_cycles; 
    uint64_t module_total_dsp_cycles_consumed; 
    uint64_t module_total_dsp_iterations; 
    uint32_t module_peak_restricted_cycles; 
    uint64_t module_total_restricted_cycles_consumed; 
    uint64_t module_total_restricted_iterations; 
} __packed __aligned(4);
 
struct extended_global_perf_data {
    uint32_t perf_item_count; 
    struct ext_perf_data_item perf_items[0]; 
} __packed __aligned(4);
 
struct perf_data_item_comp {
    struct perf_data_item item; 
    uint32_t total_iteration_count; 
    uint64_t total_cycles_consumed; 
    uint32_t restricted_peak_cycles; 
    uint64_t restricted_total_iterations; 
    uint64_t restricted_total_cycles; 
} __packed __aligned(4);
 
struct global_perf_data {
    uint32_t perf_item_count; 
    struct perf_data_item perf_items[0]; 
} __packed __aligned(4);
 
#endif /* __SOF_IPC4_BASE_FW_H__ */