IPC4 Host-DSP Protocol

Intel and AMD IPC4 protocol definitions, message structures, base firmware, gateways, and notifications. More...

Collaboration diagram for IPC4 Host-DSP Protocol:

Modules
	IPC4 Message Envelope & Dispatch
	64-bit mailbox message envelope formats, primary/extension registers, command target routing, reply status, and compound message barriers.
	IPC4 Base Firmware & Global Configuration
	Core 0 Base Firmware management, ADSP global properties, hardware capabilities, memory pools, power budget tables, and crash dump telemetry.
	IPC4 Pipeline Lifecycle & State Machine
	Pipeline creation, priority assignments, state machine transitions (RESET, PAUSED, RUNNING, EOS), multi-pipeline synchronization, and save/restore.
	IPC4 Module Architecture & Dynamic Binding
	Module instantiation, dynamic queue/pin binding, small/large parameter configuration handshake, and module power transitions.
	IPC4 Audio Formats & Pin Contracts
	Audio format specification bitfields, sampling rates, bit depths, channel configurations, and pin format descriptors.
	IPC4 Hardware Audio Gateways
	Audio gateway addressing (HD-Audio host/link, SoundWire ALH aggregation, DMIC link, SSP/I2S), gateway attributes, and NHLT configuration blobs.
	IPC4 Asynchronous Notifications & Telemetry Registers
	Unsolicited DSP-to-host notifications, resource event reports, keyword detection events, watchdog alerts, and Mailbox Window 0 status registers.
	IPC4 Telemetry, Logging & Audio Probes
	Host DMA trace logging control, audio probe injection and extraction data streams, and module-specific configuration payloads.

Files
file	schedule.h
	Host IPC message dispatch and scheduling task interface.

Detailed Description

Intel and AMD IPC4 protocol definitions, message structures, base firmware, gateways, and notifications.