Sound Open Firmware
Loading...
Searching...
No Matches
cache.h
Go to the documentation of this file.
1/* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright(c) 2022 Intel Corporation. All rights reserved.
4 */
5
12#ifndef __ZEPHYR_RTOS_CACHE_H__
13#define __ZEPHYR_RTOS_CACHE_H__
14
15#define __SOF_LIB_CACHE_H__
16
17#if !defined(__ASSEMBLER__) && !defined(LINKER)
18
19#include <zephyr/cache.h>
20#include <zephyr/debug/sparse.h>
21
22#if defined(CONFIG_XTENSA) && defined(CONFIG_INTEL)
23
24/* definitions required by xtensa-based Intel platforms.
25 *
26 * TODO: if possible, move these to Zephyr.
27 */
28#define SRAM_UNCACHED_ALIAS 0x20000000
29#define is_cached(address) (!!((uintptr_t)(address) & SRAM_UNCACHED_ALIAS))
30
31#endif /* defined(CONFIG_XTENSA) && defined(CONFIG_INTEL) */
32
33/* sanity check - make sure CONFIG_DCACHE_LINE_SIZE is valid */
34#if !defined(CONFIG_DCACHE_LINE_SIZE_DETECT) && (CONFIG_DCACHE_LINE_SIZE > 0)
35#define DCACHE_LINE_SIZE CONFIG_DCACHE_LINE_SIZE
36#else
37#if defined(CONFIG_LIBRARY) || defined(CONFIG_ZEPHYR_POSIX)
38#define DCACHE_LINE_SIZE 64
39#else
40#error "Invalid cache configuration."
41#endif /* defined(CONFIG_LIBRARY) || defined(CONFIG_ZEPHYR_POSIX) */
42#endif /* !defined(CONFIG_DCACHE_LINE_SIZE_DETECT) && (CONFIG_DCACHE_LINE_SIZE > 0) */
43
53static inline void dcache_writeback_region(void __sparse_cache *addr, size_t size)
54{
55 /* TODO: return value should probably be checked here */
56 sys_cache_data_flush_range((__sparse_force void *)addr, size);
57}
58
67static inline void dcache_invalidate_region(void __sparse_cache *addr, size_t size)
68{
69 /* TODO: return value should probably be checked here */
70 sys_cache_data_invd_range((__sparse_force void *)addr, size);
71}
72
81static inline void icache_invalidate_region(void __sparse_cache *addr, size_t size)
82{
83 /* TODO: return value should probably be checked here */
84 sys_cache_instr_invd_range((__sparse_force void *)addr, size);
85}
86
95static inline void dcache_writeback_invalidate_region(void __sparse_cache *addr, size_t size)
96{
97 /* TODO: return value should probably be checked here */
98 sys_cache_data_flush_and_invd_range((__sparse_force void *)addr, size);
99}
100
101#endif /* !defined(__ASSEMBLER__) && !defined(LINKER) */
102
103#endif /* __ZEPHYR_RTOS_CACHE_H__ */
static void dcache_writeback_invalidate_region(void *addr, size_t size)
Write back and invalidate data cache lines in the specified memory region.
Definition cache.h:95
static void dcache_writeback_region(void *addr, size_t size)
Write back (flush) modified data cache lines to memory.
Definition cache.h:53
static void icache_invalidate_region(void *addr, size_t size)
Invalidate instruction cache lines in the specified memory region.
Definition cache.h:81
static void dcache_invalidate_region(void *addr, size_t size)
Invalidate data cache lines in the specified memory region.
Definition cache.h:67