12#ifndef __ZEPHYR_RTOS_CACHE_H__
13#define __ZEPHYR_RTOS_CACHE_H__
15#define __SOF_LIB_CACHE_H__
17#if !defined(__ASSEMBLER__) && !defined(LINKER)
19#include <zephyr/cache.h>
20#include <zephyr/debug/sparse.h>
22#if defined(CONFIG_XTENSA) && defined(CONFIG_INTEL)
28#define SRAM_UNCACHED_ALIAS 0x20000000
29#define is_cached(address) (!!((uintptr_t)(address) & SRAM_UNCACHED_ALIAS))
34#if !defined(CONFIG_DCACHE_LINE_SIZE_DETECT) && (CONFIG_DCACHE_LINE_SIZE > 0)
35#define DCACHE_LINE_SIZE CONFIG_DCACHE_LINE_SIZE
37#if defined(CONFIG_LIBRARY) || defined(CONFIG_ZEPHYR_POSIX)
38#define DCACHE_LINE_SIZE 64
40#error "Invalid cache configuration."
56 sys_cache_data_flush_range((__sparse_force
void *)addr, size);
70 sys_cache_data_invd_range((__sparse_force
void *)addr, size);
84 sys_cache_instr_invd_range((__sparse_force
void *)addr, size);
98 sys_cache_data_flush_and_invd_range((__sparse_force
void *)addr, size);
static void dcache_writeback_invalidate_region(void *addr, size_t size)
Write back and invalidate data cache lines in the specified memory region.
Definition cache.h:95
static void dcache_writeback_region(void *addr, size_t size)
Write back (flush) modified data cache lines to memory.
Definition cache.h:53
static void icache_invalidate_region(void *addr, size_t size)
Invalidate instruction cache lines in the specified memory region.
Definition cache.h:81
static void dcache_invalidate_region(void *addr, size_t size)
Invalidate data cache lines in the specified memory region.
Definition cache.h:67