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cache.h
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1/* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright(c) 2022 Intel Corporation. All rights reserved.
4 */
5
6#ifndef __ZEPHYR_RTOS_CACHE_H__
7#define __ZEPHYR_RTOS_CACHE_H__
8
9#define __SOF_LIB_CACHE_H__
10
11#if !defined(__ASSEMBLER__) && !defined(LINKER)
12
13#include <zephyr/cache.h>
14#include <zephyr/debug/sparse.h>
15
16#if defined(CONFIG_XTENSA) && defined(CONFIG_INTEL)
17
18/* definitions required by xtensa-based Intel platforms.
19 *
20 * TODO: if possible, move these to Zephyr.
21 */
22#define SRAM_UNCACHED_ALIAS 0x20000000
23#define is_cached(address) (!!((uintptr_t)(address) & SRAM_UNCACHED_ALIAS))
24
25#endif /* defined(CONFIG_XTENSA) && defined(CONFIG_INTEL) */
26
27/* sanity check - make sure CONFIG_DCACHE_LINE_SIZE is valid */
28#if !defined(CONFIG_DCACHE_LINE_SIZE_DETECT) && (CONFIG_DCACHE_LINE_SIZE > 0)
29#define DCACHE_LINE_SIZE CONFIG_DCACHE_LINE_SIZE
30#else
31#if defined(CONFIG_LIBRARY) || defined(CONFIG_ZEPHYR_POSIX)
32#define DCACHE_LINE_SIZE 64
33#else
34#error "Invalid cache configuration."
35#endif /* defined(CONFIG_LIBRARY) || defined(CONFIG_ZEPHYR_POSIX) */
36#endif /* !defined(CONFIG_DCACHE_LINE_SIZE_DETECT) && (CONFIG_DCACHE_LINE_SIZE > 0) */
37
38static inline void dcache_writeback_region(void __sparse_cache *addr, size_t size)
39{
40 /* TODO: return value should probably be checked here */
41 sys_cache_data_flush_range((__sparse_force void *)addr, size);
42}
43
44static inline void dcache_invalidate_region(void __sparse_cache *addr, size_t size)
45{
46 /* TODO: return value should probably be checked here */
47 sys_cache_data_invd_range((__sparse_force void *)addr, size);
48}
49
50static inline void icache_invalidate_region(void __sparse_cache *addr, size_t size)
51{
52 /* TODO: return value should probably be checked here */
53 sys_cache_instr_invd_range((__sparse_force void *)addr, size);
54}
55
56static inline void dcache_writeback_invalidate_region(void __sparse_cache *addr, size_t size)
57{
58 /* TODO: return value should probably be checked here */
59 sys_cache_data_flush_and_invd_range((__sparse_force void *)addr, size);
60}
61
62#endif /* !defined(__ASSEMBLER__) && !defined(LINKER) */
63
64#endif /* __ZEPHYR_RTOS_CACHE_H__ */
static void dcache_writeback_invalidate_region(void __sparse_cache *addr, size_t size)
Definition cache.h:56
static void icache_invalidate_region(void __sparse_cache *addr, size_t size)
Definition cache.h:50
static void dcache_writeback_region(void __sparse_cache *addr, size_t size)
Definition cache.h:38
static void dcache_invalidate_region(void __sparse_cache *addr, size_t size)
Definition cache.h:44
#define __sparse_force
Definition compiler_attributes.h:12
#define __sparse_cache
Definition compiler_attributes.h:11