RTOS data and instruction cache invalidation and writeback helpers.
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RTOS data and instruction cache invalidation and writeback helpers.
◆ __SOF_LIB_CACHE_H__
| #define __SOF_LIB_CACHE_H__ |
◆ dcache_invalidate_region()
| static void dcache_invalidate_region |
( |
void * |
addr, |
|
|
size_t |
size |
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) |
| |
|
inlinestatic |
Invalidate data cache lines in the specified memory region.
- Parameters
-
| addr | Starting address of the memory region to invalidate. |
| size | Size in bytes of the region to invalidate. |
Discards cached data lines covering the address range so subsequent reads fetch fresh data directly from physical SRAM or DMA-updated memory.
◆ dcache_writeback_invalidate_region()
| static void dcache_writeback_invalidate_region |
( |
void * |
addr, |
|
|
size_t |
size |
|
) |
| |
|
inlinestatic |
Write back and invalidate data cache lines in the specified memory region.
- Parameters
-
| addr | Starting address of the memory region. |
| size | Size in bytes of the region. |
Flushes modified cache lines back to memory and then invalidates them. Typically used for bidirectional DMA buffers or when reallocating SRAM pools.
◆ dcache_writeback_region()
| static void dcache_writeback_region |
( |
void * |
addr, |
|
|
size_t |
size |
|
) |
| |
|
inlinestatic |
Write back (flush) modified data cache lines to memory.
- Parameters
-
| addr | Starting address of the memory region to flush. |
| size | Size in bytes of the region to flush. |
Flushes dirty lines in the data cache covering the specified address range back to physical memory or SRAM. Mandatory before handing buffers over to hardware DMA or notifying peer cores / host.
◆ icache_invalidate_region()
| static void icache_invalidate_region |
( |
void * |
addr, |
|
|
size_t |
size |
|
) |
| |
|
inlinestatic |
Invalidate instruction cache lines in the specified memory region.
- Parameters
-
| addr | Starting address of the code memory region to invalidate. |
| size | Size in bytes of the code region. |
Used after dynamically loading or relocating executable code (e.g. LLEXT modules) to ensure the instruction pipeline does not execute stale instructions.