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cpu.h
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1/* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright(c) 2018 Intel Corporation. All rights reserved.
4 *
5 * Author: Tomasz Leman <tomasz.m.leman@intel.com>
6 */
7
13
14#ifndef __SOF_LIB_CPU_H__
15#define __SOF_LIB_CPU_H__
16
25#define PLATFORM_PRIMARY_CORE_ID 0
26
27#if !defined(__ASSEMBLER__) && !defined(LINKER)
28
29#include <stdbool.h>
30
31#include <zephyr/arch/arch_inlines.h>
32
33#if CONFIG_PM
34
35#include <zephyr/pm/pm.h>
36
37void cpu_notify_state_entry(enum pm_state state);
38
39void cpu_notify_state_exit(enum pm_state state);
40
41#endif /* CONFIG_PM */
42
43/*
44 * cpu_get_id() is exposed as a Zephyr system call so that user-mode
45 * threads (e.g. user-space LL pipelines) can query the current core
46 * id. The underlying arch_proc_id() reads a privileged special
47 * register (e.g. Xtensa PRID) which would fault if executed directly
48 * from user mode. In supervisor context the generated wrapper inlines
49 * the z_impl_cpu_get_id() body, so there is no overhead there.
50 */
51#if defined(CONFIG_SOF_FULL_ZEPHYR_APPLICATION)
52__syscall int cpu_get_id(void);
53#endif
54
55/* let the compiler optimise when in single core mode */
56#if CONFIG_MULTICORE && CONFIG_SMP
57
58#if defined(CONFIG_SOF_FULL_ZEPHYR_APPLICATION)
59static inline int z_impl_cpu_get_id(void)
60{
61 return arch_proc_id();
62}
63#else
64static inline int cpu_get_id(void)
65{
66 return arch_proc_id();
67}
68#endif
69
70static inline bool cpu_is_primary(int id)
71{
72 return id == PLATFORM_PRIMARY_CORE_ID;
73}
74
75static inline bool cpu_is_me(int id)
76{
77 return id == cpu_get_id();
78}
79
80int cpu_enable_core(int id);
81
82void cpu_disable_core(int id);
83
84int cpu_is_core_enabled(int id);
85
86int cpu_enabled_cores(void);
87
88void cpu_power_down_core(uint32_t flags);
89
91
93#else
94
95#if defined(CONFIG_SOF_FULL_ZEPHYR_APPLICATION)
96static inline int z_impl_cpu_get_id(void) { return 0; };
97#else
98static inline int cpu_get_id(void) { return 0; };
99#endif
100
101static inline bool cpu_is_primary(int id) { return 1; };
102
103static inline bool cpu_is_me(int id) { return 1; };
104
105static inline int cpu_enable_core(int id) { return 0; };
106
107static inline void cpu_disable_core(int id) { };
108
109static inline int cpu_is_core_enabled(int id) { return 1; };
110
111static inline int cpu_enabled_cores(void) { return 1; };
112
113static inline int cpu_restore_secondary_cores(void) { return 0; };
114
115static inline int cpu_secondary_cores_prepare_d0ix(void) { return 0; };
116
117#endif /* CONFIG_MULTICORE && CONFIG_SMP */
118
119#if defined(CONFIG_SOF_FULL_ZEPHYR_APPLICATION)
120#include <zephyr/syscalls/cpu.h>
121#endif
122
123#endif
124
125#endif /* __SOF_LIB_CPU_H__ */
static int cpu_is_core_enabled(int id)
Definition cpu.h:109
static void cpu_disable_core(int id)
Definition cpu.h:107
static bool cpu_is_me(int id)
Definition cpu.h:103
static int cpu_enabled_cores(void)
Definition cpu.h:111
#define PLATFORM_PRIMARY_CORE_ID
Id of primary DSP core.
Definition cpu.h:25
static int cpu_secondary_cores_prepare_d0ix(void)
Definition cpu.h:115
static bool cpu_is_primary(int id)
Definition cpu.h:101
static int cpu_restore_secondary_cores(void)
Definition cpu.h:113
static int cpu_enable_core(int id)
Definition cpu.h:105
static int cpu_get_id(void)
Definition cpu.h:98