edma.h File Reference

Include dependency graph for edma.h:

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Macros
#define	EDMA_CH_CSR   0x00
#define	EDMA_CH_ES   0x04
#define	EDMA_CH_INT   0x08
#define	EDMA_CH_SBR   0x0C
#define	EDMA_CH_PRI   0x10
#define	EDMA_CH_MUX   0x14
#define	EDMA_TCD_SADDR   0x20
#define	EDMA_TCD_SOFF   0x24
#define	EDMA_TCD_ATTR   0x26
#define	EDMA_TCD_NBYTES   0x28
#define	EDMA_TCD_SLAST   0x2C
#define	EDMA_TCD_DADDR   0x30
#define	EDMA_TCD_DOFF   0x34
#define	EDMA_TCD_CITER_ELINK   0x36
#define	EDMA_TCD_CITER   0x36
#define	EDMA_TCD_DLAST_SGA   0x38
#define	EDMA_TCD_CSR   0x3C
#define	EDMA_TCD_BITER_ELINK   0x3E
#define	EDMA_TCD_BITER   0x3E
#define	EDMA_CSR   0x00
#define	EDMA_ES   0x04
#define	EDMA_INT   0x08
#define	EDMA_HRS   0x0C
#define	EDMA_TCD_CSR_START   BIT(0)
#define	EDMA_TCD_CSR_INTMAJOR   BIT(1)
#define	EDMA_TCD_CSR_INTHALF   BIT(2)
#define	EDMA_TCD_CSR_INTHALF_INTMAJOR   (BIT(1) | BIT(2))
#define	EDMA_TCD_CSR_DREQ   BIT(3)
#define	EDMA_TCD_CSR_ESG   BIT(4)
#define	EDMA_CH_CSR_ERQ_EARQ   (BIT(0) | BIT(1))
#define	EDMA_CH_ES_ERR   BIT(31)
#define	EDMA_CH_ES_SAE   BIT(7)
#define	EDMA_CH_ES_SOE   BIT(6)
#define	EDMA_CH_ES_DAE   BIT(5)
#define	EDMA_CH_ES_DOE   BIT(4)
#define	EDMA_CH_ES_NCE   BIT(3)
#define	EDMA_CH_ES_SGE   BIT(2)
#define	EDMA_CH_ES_SBE   BIT(1)
#define	EDMA_CH_ES_DBE   BIT(0)
#define	EDMA_TCD_ATTR_SSIZE_8BIT   0x0000
#define	EDMA_TCD_ATTR_SSIZE_16BIT   0x0100
#define	EDMA_TCD_ATTR_SSIZE_32BIT   0x0200
#define	EDMA_TCD_ATTR_SSIZE_64BIT   0x0300
#define	EDMA_TCD_ATTR_SSIZE_16BYTE   0x0400
#define	EDMA_TCD_ATTR_SSIZE_32BYTE   0x0500
#define	EDMA_TCD_ATTR_SSIZE_64BYTE   0x0600
#define	EDMA_TCD_ATTR_DSIZE_8BIT   0x0000
#define	EDMA_TCD_ATTR_DSIZE_16BIT   0x0001
#define	EDMA_TCD_ATTR_DSIZE_32BIT   0x0002
#define	EDMA_TCD_ATTR_DSIZE_64BIT   0x0003
#define	EDMA_TCD_ATTR_DSIZE_16BYTE   0x0004
#define	EDMA_TCD_ATTR_DSIZE_32BYTE   0x0005
#define	EDMA_TCD_ATTR_DSIZE_64BYTE   0x0006
#define	EDMA_BUFFER_PERIOD_COUNT   2
#define	EDMA_TCD_ALIGNMENT   32
#define	EDMA_HS_GET_IRQ(hs)
#define	EDMA_HS_SET_IRQ(irq)
#define	EDMA_HS_GET_CHAN(hs)
#define	EDMA_HS_SET_CHAN(chan)
#define	EDMA_HS_GET_DMAMUX_CFG(hs)
#define	EDMA_HS_SET_DMAMUX_CFG(cfg)
#define	EDMA_HANDSHAKE(irq, channel, cfg)
#define	EDMA0_ESAI_CHAN_RX   6
#define	EDMA0_ESAI_CHAN_TX   7
#define	EDMA0_SAI_CHAN_RX   14
#define	EDMA0_SAI_CHAN_TX   15
#define	EDMA0_CHAN_MAX   32
#define	EDMA0_ESAI_CHAN_RX_IRQ   442
#define	EDMA0_ESAI_CHAN_TX_IRQ   442
#define	EDMA0_SAI_CHAN_RX_IRQ   349
#define	EDMA0_SAI_CHAN_TX_IRQ   349
#define	IMX8ULP_EDMA2_CHAN0   0
#define	IMX8ULP_EDMA2_CHAN1   1
#define	IMX8ULP_EDMA2_CHAN_MAX   8
#define	IMX8ULP_EDMA2_CHAN0_IRQ   6
#define	IMX8ULP_EDMA2_CHAN1_IRQ   7
#define	IMX8ULP_EDMA2_CHAN2_IRQ   8
#define	IMX8ULP_EDMA2_CHAN3_IRQ   9
#define	IMX8ULP_EDMA2_CHAN4_IRQ   10
#define	IMX8ULP_EDMA2_CHAN5_IRQ   11
#define	IMX8ULP_EDMA2_CHAN6_IRQ   12
#define	IMX8ULP_EDMA2_CHAN7_IRQ   13
#define	IMX8ULP_DMAMUX2_SAI5_RX   69
#define	IMX8ULP_DMAMUX2_SAI5_TX   70
#define	IMX8ULP_DMAMUX2_SAI6_RX   71
#define	IMX8ULP_DMAMUX2_SAI6_TX   72

Macro Definition Documentation

EDMA0_CHAN_MAX

#define EDMA0_CHAN_MAX   32

EDMA0_ESAI_CHAN_RX

#define EDMA0_ESAI_CHAN_RX   6

EDMA0_ESAI_CHAN_RX_IRQ

#define EDMA0_ESAI_CHAN_RX_IRQ   442

EDMA0_ESAI_CHAN_TX

#define EDMA0_ESAI_CHAN_TX   7

EDMA0_ESAI_CHAN_TX_IRQ

#define EDMA0_ESAI_CHAN_TX_IRQ   442

EDMA0_SAI_CHAN_RX

#define EDMA0_SAI_CHAN_RX   14

EDMA0_SAI_CHAN_RX_IRQ

#define EDMA0_SAI_CHAN_RX_IRQ   349

EDMA0_SAI_CHAN_TX

#define EDMA0_SAI_CHAN_TX   15

EDMA0_SAI_CHAN_TX_IRQ

#define EDMA0_SAI_CHAN_TX_IRQ   349

EDMA_BUFFER_PERIOD_COUNT

#define EDMA_BUFFER_PERIOD_COUNT   2

EDMA_CH_CSR

#define EDMA_CH_CSR   0x00

EDMA_CH_CSR_ERQ_EARQ

#define EDMA_CH_CSR_ERQ_EARQ   (BIT(0) | BIT(1))

EDMA_CH_ES

#define EDMA_CH_ES   0x04

EDMA_CH_ES_DAE

#define EDMA_CH_ES_DAE   BIT(5)

EDMA_CH_ES_DBE

#define EDMA_CH_ES_DBE   BIT(0)

EDMA_CH_ES_DOE

#define EDMA_CH_ES_DOE   BIT(4)

EDMA_CH_ES_ERR

#define EDMA_CH_ES_ERR   BIT(31)

EDMA_CH_ES_NCE

#define EDMA_CH_ES_NCE   BIT(3)

EDMA_CH_ES_SAE

#define EDMA_CH_ES_SAE   BIT(7)

EDMA_CH_ES_SBE

#define EDMA_CH_ES_SBE   BIT(1)

EDMA_CH_ES_SGE

#define EDMA_CH_ES_SGE   BIT(2)

EDMA_CH_ES_SOE

#define EDMA_CH_ES_SOE   BIT(6)

EDMA_CH_INT

#define EDMA_CH_INT   0x08

EDMA_CH_MUX

#define EDMA_CH_MUX   0x14

EDMA_CH_PRI

#define EDMA_CH_PRI   0x10

EDMA_CH_SBR

#define EDMA_CH_SBR   0x0C

EDMA_CSR

#define EDMA_CSR   0x00

EDMA_ES

#define EDMA_ES   0x04

EDMA_HANDSHAKE

#define EDMA_HANDSHAKE	(		irq,
			channel,
			cfg )

Value:

    (EDMA_HS_SET_CHAN(channel) | EDMA_HS_SET_IRQ(irq) | EDMA_HS_SET_DMAMUX_CFG(cfg))

EDMA_HRS

#define EDMA_HRS   0x0C

EDMA_HS_GET_CHAN

#define EDMA_HS_GET_CHAN

(

hs

)

Value:

(((hs) & MASK(13, 9)) >> 9)

EDMA_HS_GET_DMAMUX_CFG

#define EDMA_HS_GET_DMAMUX_CFG

(

hs

)

Value:

(((hs) & MASK(21, 14)) >> 14)

EDMA_HS_GET_IRQ

#define EDMA_HS_GET_IRQ

(

hs

)

Value:

(((hs) & MASK(8, 0)) >> 0)

EDMA_HS_SET_CHAN

#define EDMA_HS_SET_CHAN

(

chan

)

Value:

SET_BITS(13, 9, chan)

EDMA_HS_SET_DMAMUX_CFG

#define EDMA_HS_SET_DMAMUX_CFG

(

cfg

)

Value:

SET_BITS(21, 14, cfg)

EDMA_HS_SET_IRQ

#define EDMA_HS_SET_IRQ

(

irq

)

Value:

SET_BITS(8, 0, irq)

EDMA_INT

#define EDMA_INT   0x08

EDMA_TCD_ALIGNMENT

#define EDMA_TCD_ALIGNMENT   32

EDMA_TCD_ATTR

#define EDMA_TCD_ATTR   0x26

EDMA_TCD_ATTR_DSIZE_16BIT

#define EDMA_TCD_ATTR_DSIZE_16BIT   0x0001

EDMA_TCD_ATTR_DSIZE_16BYTE

#define EDMA_TCD_ATTR_DSIZE_16BYTE   0x0004

EDMA_TCD_ATTR_DSIZE_32BIT

#define EDMA_TCD_ATTR_DSIZE_32BIT   0x0002

EDMA_TCD_ATTR_DSIZE_32BYTE

#define EDMA_TCD_ATTR_DSIZE_32BYTE   0x0005

EDMA_TCD_ATTR_DSIZE_64BIT

#define EDMA_TCD_ATTR_DSIZE_64BIT   0x0003

EDMA_TCD_ATTR_DSIZE_64BYTE

#define EDMA_TCD_ATTR_DSIZE_64BYTE   0x0006

EDMA_TCD_ATTR_DSIZE_8BIT

#define EDMA_TCD_ATTR_DSIZE_8BIT   0x0000

EDMA_TCD_ATTR_SSIZE_16BIT

#define EDMA_TCD_ATTR_SSIZE_16BIT   0x0100

EDMA_TCD_ATTR_SSIZE_16BYTE

#define EDMA_TCD_ATTR_SSIZE_16BYTE   0x0400

EDMA_TCD_ATTR_SSIZE_32BIT

#define EDMA_TCD_ATTR_SSIZE_32BIT   0x0200

EDMA_TCD_ATTR_SSIZE_32BYTE

#define EDMA_TCD_ATTR_SSIZE_32BYTE   0x0500

EDMA_TCD_ATTR_SSIZE_64BIT

#define EDMA_TCD_ATTR_SSIZE_64BIT   0x0300

EDMA_TCD_ATTR_SSIZE_64BYTE

#define EDMA_TCD_ATTR_SSIZE_64BYTE   0x0600

EDMA_TCD_ATTR_SSIZE_8BIT

#define EDMA_TCD_ATTR_SSIZE_8BIT   0x0000

EDMA_TCD_BITER

#define EDMA_TCD_BITER   0x3E

EDMA_TCD_BITER_ELINK

#define EDMA_TCD_BITER_ELINK   0x3E

EDMA_TCD_CITER

#define EDMA_TCD_CITER   0x36

EDMA_TCD_CITER_ELINK

#define EDMA_TCD_CITER_ELINK   0x36

EDMA_TCD_CSR

#define EDMA_TCD_CSR   0x3C

EDMA_TCD_CSR_DREQ

#define EDMA_TCD_CSR_DREQ   BIT(3)

EDMA_TCD_CSR_ESG

#define EDMA_TCD_CSR_ESG   BIT(4)

EDMA_TCD_CSR_INTHALF

#define EDMA_TCD_CSR_INTHALF   BIT(2)

EDMA_TCD_CSR_INTHALF_INTMAJOR

#define EDMA_TCD_CSR_INTHALF_INTMAJOR   (BIT(1) | BIT(2))

EDMA_TCD_CSR_INTMAJOR

#define EDMA_TCD_CSR_INTMAJOR   BIT(1)

EDMA_TCD_CSR_START

#define EDMA_TCD_CSR_START   BIT(0)

EDMA_TCD_DADDR

#define EDMA_TCD_DADDR   0x30

EDMA_TCD_DLAST_SGA

#define EDMA_TCD_DLAST_SGA   0x38

EDMA_TCD_DOFF

#define EDMA_TCD_DOFF   0x34

EDMA_TCD_NBYTES

#define EDMA_TCD_NBYTES   0x28

EDMA_TCD_SADDR

#define EDMA_TCD_SADDR   0x20

EDMA_TCD_SLAST

#define EDMA_TCD_SLAST   0x2C

EDMA_TCD_SOFF

#define EDMA_TCD_SOFF   0x24

IMX8ULP_DMAMUX2_SAI5_RX

#define IMX8ULP_DMAMUX2_SAI5_RX   69

IMX8ULP_DMAMUX2_SAI5_TX

#define IMX8ULP_DMAMUX2_SAI5_TX   70

IMX8ULP_DMAMUX2_SAI6_RX

#define IMX8ULP_DMAMUX2_SAI6_RX   71

IMX8ULP_DMAMUX2_SAI6_TX

#define IMX8ULP_DMAMUX2_SAI6_TX   72

IMX8ULP_EDMA2_CHAN0

#define IMX8ULP_EDMA2_CHAN0   0

IMX8ULP_EDMA2_CHAN0_IRQ

#define IMX8ULP_EDMA2_CHAN0_IRQ   6

IMX8ULP_EDMA2_CHAN1

#define IMX8ULP_EDMA2_CHAN1   1

IMX8ULP_EDMA2_CHAN1_IRQ

#define IMX8ULP_EDMA2_CHAN1_IRQ   7

IMX8ULP_EDMA2_CHAN2_IRQ

#define IMX8ULP_EDMA2_CHAN2_IRQ   8

IMX8ULP_EDMA2_CHAN3_IRQ

#define IMX8ULP_EDMA2_CHAN3_IRQ   9

IMX8ULP_EDMA2_CHAN4_IRQ

#define IMX8ULP_EDMA2_CHAN4_IRQ   10

IMX8ULP_EDMA2_CHAN5_IRQ

#define IMX8ULP_EDMA2_CHAN5_IRQ   11

IMX8ULP_EDMA2_CHAN6_IRQ

#define IMX8ULP_EDMA2_CHAN6_IRQ   12

IMX8ULP_EDMA2_CHAN7_IRQ

#define IMX8ULP_EDMA2_CHAN7_IRQ   13

IMX8ULP_EDMA2_CHAN_MAX

#define IMX8ULP_EDMA2_CHAN_MAX   8