esai.h File Reference

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Go to the source code of this file.

Macros
#define	REG_ESAI_ETDR   0x00
#define	REG_ESAI_ERDR   0x04
#define	REG_ESAI_ECR   0x08
#define	REG_ESAI_ESR   0x0C
#define	REG_ESAI_TFCR   0x10
#define	REG_ESAI_TFSR   0x14
#define	REG_ESAI_RFCR   0x18
#define	REG_ESAI_RFSR   0x1C
#define	REG_ESAI_xFCR(rx)
#define	REG_ESAI_xFSR(rx)
#define	REG_ESAI_TX0   0x80
#define	REG_ESAI_TX1   0x84
#define	REG_ESAI_TX2   0x88
#define	REG_ESAI_TX3   0x8C
#define	REG_ESAI_TX4   0x90
#define	REG_ESAI_TX5   0x94
#define	REG_ESAI_TSR   0x98
#define	REG_ESAI_RX0   0xA0
#define	REG_ESAI_RX1   0xA4
#define	REG_ESAI_RX2   0xA8
#define	REG_ESAI_RX3   0xAC
#define	REG_ESAI_SAISR   0xCC
#define	REG_ESAI_SAICR   0xD0
#define	REG_ESAI_TCR   0xD4
#define	REG_ESAI_TCCR   0xD8
#define	REG_ESAI_RCR   0xDC
#define	REG_ESAI_RCCR   0xE0
#define	REG_ESAI_xCR(rx)
#define	REG_ESAI_xCCR(rx)
#define	REG_ESAI_TSMA   0xE4
#define	REG_ESAI_TSMB   0xE8
#define	REG_ESAI_RSMA   0xEC
#define	REG_ESAI_RSMB   0xF0
#define	REG_ESAI_xSMA(rx)
#define	REG_ESAI_xSMB(rx)
#define	REG_ESAI_PRRC   0xF8
#define	REG_ESAI_PCRC   0xFC
#define	ESAI_ECR_ETI   BIT(19)
#define	ESAI_ECR_ETO   BIT(18)
#define	ESAI_ECR_ERI   BIT(17)
#define	ESAI_ECR_ERO   BIT(16)
#define	ESAI_ECR_ERST   BIT(1)
#define	ESAI_ECR_ESAIEN   BIT(0)
#define	ESAI_ESR_TINIT   BIT(10)
#define	ESAI_ESR_RFF   BIT(9)
#define	ESAI_ESR_TFE   BIT(8)
#define	ESAI_ESR_TLS   BIT(7)
#define	ESAI_ESR_TDE   BIT(6)
#define	ESAI_ESR_TED   BIT(5)
#define	ESAI_ESR_TD   BIT(4)
#define	ESAI_ESR_RLS   BIT(3)
#define	ESAI_ESR_RDE   BIT(2)
#define	ESAI_ESR_RED   BIT(1)
#define	ESAI_ESR_RD   BIT(0)
#define	ESAI_xFCR_TIEN   BIT(19)
#define	ESAI_xFCR_xWA_SHIFT   16
#define	ESAI_xFCR_xWA_WIDTH   3
#define	ESAI_xFCR_xWA_MASK   MASK(18, 16)
#define	ESAI_xFCR_xWA(v)
#define	ESAI_xFCR_xFWM_SHIFT   8
#define	ESAI_xFCR_xFWM_WIDTH   8
#define	ESAI_xFCR_xFWM_MASK   MASK(15, 8)
#define	ESAI_xFCR_xFWM(v)
#define	ESAI_xFCR_xE_SHIFT   2
#define	ESAI_xFCR_TE_WIDTH   6
#define	ESAI_xFCR_RE_WIDTH   4
#define	ESAI_xFCR_TE_MASK   MASK(7, 2)
#define	ESAI_xFCR_RE_MASK   MASK(5, 2)
#define	ESAI_xFCR_xE_MASK(rx)
#define	ESAI_xFCR_TE(x)
#define	ESAI_xFCR_RE(x)
#define	ESAI_xFCR_xE(rx, x)
#define	ESAI_xFCR_xFR_SHIFT   1
#define	ESAI_xFCR_xFR_MASK   BIT(1)
#define	ESAI_xFCR_xFR   BIT(1)
#define	ESAI_xFCR_xFEN_SHIFT   0
#define	ESAI_xFCR_xFEN   BIT(0)
#define	ESAI_xFCR_xFEN_MASK   BIT(0)
#define	ESAI_xFSR_NTFO_MASK   MASK(14, 12)
#define	ESAI_xFSR_NTFI_MASK   MASK(10, 8)
#define	ESAI_xFSR_NRFO_MASK   MASK(9, 8)
#define	ESAI_xFSR_NRFI_MASK   MASK(13, 12)
#define	ESAI_xFSR_xFCNT_MASK   MASK(7, 0)
#define	ESAI_SAISR_TODFE   BIT(17)
#define	ESAI_SAISR_TEDE   BIT(16)
#define	ESAI_SAISR_TDE   BIT(15)
#define	ESAI_SAISR_TUE   BIT(14)
#define	ESAI_SAISR_TFS   BIT(13)
#define	ESAI_SAISR_RODF   BIT(10)
#define	ESAI_SAISR_REDF   BIT(9)
#define	ESAI_SAISR_RDF   BIT(8)
#define	ESAI_SAISR_ROE   BIT(7)
#define	ESAI_SAISR_RFS   BIT(6)
#define	ESAI_SAISR_IF2   BIT(2)
#define	ESAI_SAISR_IF1   BIT(1)
#define	ESAI_SAISR_IF0   BIT(0)
#define	ESAI_SAICR_ALC   BIT(8)
#define	ESAI_SAICR_TEBE   BIT(7)
#define	ESAI_SAICR_SYN   BIT(6)
#define	ESAI_SAICR_OF2   BIT(2)
#define	ESAI_SAICR_OF1   BIT(1)
#define	ESAI_SAICR_OF0   BIT(0)
#define	ESAI_xCR_xLIE   BIT(23)
#define	ESAI_xCR_xIE   BIT(22)
#define	ESAI_xCR_xEDIE   BIT(21)
#define	ESAI_xCR_xEIE   BIT(20)
#define	ESAI_xCR_xPR   BIT(19)
#define	ESAI_xCR_PADC   BIT(17) /* only valid on tx */
#define	ESAI_xCR_xFSR   BIT(16)
#define	ESAI_xCR_xFSL   BIT(15)
#define	ESAI_xCR_xSWS_MASK   MASK(14, 10)
#define	ESAI_xCR_xSWS_VAL(s, w)
#define	ESAI_xCR_xSWS(s, w)
#define	ESAI_xCR_xMOD_MASK   MASK(9, 8)
#define	ESAI_xCR_xMOD_NORMAL   SET_BITS(9, 8, 0)
#define	ESAI_xCR_xMOD_NETWORK   SET_BITS(9, 8, 1)
#define	ESAI_xCR_xMOD_AC97   SET_BITS(9, 8, 3)
#define	ESAI_xCR_xWA   BIT(7)
#define	ESAI_xCR_xSHFD   BIT(6)
#define	ESAI_xCR_TE_MASK   MASK(5, 0)
#define	ESAI_xCR_TE_SET(v)
#define	ESAI_xCR_TE(v)
#define	ESAI_xCR_RE_MASK   MASK(3, 0)
#define	ESAI_xCR_RE_SET(v)
#define	ESAI_xCR_RE(v)
#define	ESAI_xCR_xE_MASK(rx)
#define	ESAI_xCR_xE(rx, v)
#define	ESAI_xCCR_xHCKD   BIT(23)
#define	ESAI_xCCR_xFSD   BIT(22)
#define	ESAI_xCCR_xCKD   BIT(21)
#define	ESAI_xCCR_xHCKP   BIT(20)
#define	ESAI_xCCR_xFSP   BIT(19)
#define	ESAI_xCCR_xCKP   BIT(18)
#define	ESAI_xCCR_xFP_MASK   MASK(17, 14)
#define	ESAI_xCCR_xFP(div)
#define	ESAI_xCCR_xDC_MASK   MASK(13, 9)
#define	ESAI_xCCR_xDC(v)
#define	ESAI_xCCR_xDC_AC97   SET_BITS(13, 9, 0x0C)
#define	ESAI_xCCR_xPSR_MASK   MASK(8, 8)
#define	ESAI_xCCR_xPSR_BYPASS   SET_BITS(8, 8, 1)
#define	ESAI_xCCR_xPSR_DIV8   SET_BITS(8, 8, 0)
#define	ESAI_xCCR_xPM_MASK   MASK(7, 0)
#define	ESAI_xCCR_xPM(v)
#define	ESAI_xSMA_xS_MASK   MASK(15, 0)
#define	ESAI_xSMA_xS(v)
#define	ESAI_xSMB_xS_MASK   MASK(15, 0)
#define	ESAI_xSMB_xS(v)
#define	ESAI_xSMA_xS_CHANS(ch)
#define	ESAI_xSMB_xS_CHANS(ch)
#define	ESAI_PRRC_PDC_MASK   MASK(11, 0)
#define	ESAI_PRRC_PDC(v)
#define	ESAI_PCRC_PC_MASK   MASK(11, 0)
#define	ESAI_PCRC_PC(v)
#define	ESAI_GPIO   MASK(11, 0)
#define	EDMA_ESAI_IRQ   442
#define	EDMA_ESAI_TX_CHAN   7
#define	EDMA_ESAI_RX_CHAN   6

Variables
const struct dai_driver	esai_driver

Macro Definition Documentation

EDMA_ESAI_IRQ

#define EDMA_ESAI_IRQ   442

EDMA_ESAI_RX_CHAN

#define EDMA_ESAI_RX_CHAN   6

EDMA_ESAI_TX_CHAN

#define EDMA_ESAI_TX_CHAN   7

ESAI_ECR_ERI

#define ESAI_ECR_ERI   BIT(17)

ESAI_ECR_ERO

#define ESAI_ECR_ERO   BIT(16)

ESAI_ECR_ERST

#define ESAI_ECR_ERST   BIT(1)

ESAI_ECR_ESAIEN

#define ESAI_ECR_ESAIEN   BIT(0)

ESAI_ECR_ETI

#define ESAI_ECR_ETI   BIT(19)

ESAI_ECR_ETO

#define ESAI_ECR_ETO   BIT(18)

ESAI_ESR_RD

#define ESAI_ESR_RD   BIT(0)

ESAI_ESR_RDE

#define ESAI_ESR_RDE   BIT(2)

ESAI_ESR_RED

#define ESAI_ESR_RED   BIT(1)

ESAI_ESR_RFF

#define ESAI_ESR_RFF   BIT(9)

ESAI_ESR_RLS

#define ESAI_ESR_RLS   BIT(3)

ESAI_ESR_TD

#define ESAI_ESR_TD   BIT(4)

ESAI_ESR_TDE

#define ESAI_ESR_TDE   BIT(6)

ESAI_ESR_TED

#define ESAI_ESR_TED   BIT(5)

ESAI_ESR_TFE

#define ESAI_ESR_TFE   BIT(8)

ESAI_ESR_TINIT

#define ESAI_ESR_TINIT   BIT(10)

ESAI_ESR_TLS

#define ESAI_ESR_TLS   BIT(7)

ESAI_GPIO

#define ESAI_GPIO   MASK(11, 0)

ESAI_PCRC_PC

#define ESAI_PCRC_PC

(

v

)

Value:

SET_BITS(11, 0, v)

ESAI_PCRC_PC_MASK

#define ESAI_PCRC_PC_MASK   MASK(11, 0)

ESAI_PRRC_PDC

#define ESAI_PRRC_PDC

(

v

)

Value:

SET_BITS(11, 0, v)

ESAI_PRRC_PDC_MASK

#define ESAI_PRRC_PDC_MASK   MASK(11, 0)

ESAI_SAICR_ALC

#define ESAI_SAICR_ALC   BIT(8)

ESAI_SAICR_OF0

#define ESAI_SAICR_OF0   BIT(0)

ESAI_SAICR_OF1

#define ESAI_SAICR_OF1   BIT(1)

ESAI_SAICR_OF2

#define ESAI_SAICR_OF2   BIT(2)

ESAI_SAICR_SYN

#define ESAI_SAICR_SYN   BIT(6)

ESAI_SAICR_TEBE

#define ESAI_SAICR_TEBE   BIT(7)

ESAI_SAISR_IF0

#define ESAI_SAISR_IF0   BIT(0)

ESAI_SAISR_IF1

#define ESAI_SAISR_IF1   BIT(1)

ESAI_SAISR_IF2

#define ESAI_SAISR_IF2   BIT(2)

ESAI_SAISR_RDF

#define ESAI_SAISR_RDF   BIT(8)

ESAI_SAISR_REDF

#define ESAI_SAISR_REDF   BIT(9)

ESAI_SAISR_RFS

#define ESAI_SAISR_RFS   BIT(6)

ESAI_SAISR_RODF

#define ESAI_SAISR_RODF   BIT(10)

ESAI_SAISR_ROE

#define ESAI_SAISR_ROE   BIT(7)

ESAI_SAISR_TDE

#define ESAI_SAISR_TDE   BIT(15)

ESAI_SAISR_TEDE

#define ESAI_SAISR_TEDE   BIT(16)

ESAI_SAISR_TFS

#define ESAI_SAISR_TFS   BIT(13)

ESAI_SAISR_TODFE

#define ESAI_SAISR_TODFE   BIT(17)

ESAI_SAISR_TUE

#define ESAI_SAISR_TUE   BIT(14)

ESAI_xCCR_xCKD

#define ESAI_xCCR_xCKD   BIT(21)

ESAI_xCCR_xCKP

#define ESAI_xCCR_xCKP   BIT(18)

ESAI_xCCR_xDC

#define ESAI_xCCR_xDC

(

v

)

Value:

SET_BITS(13, 9, (v) - 1)

ESAI_xCCR_xDC_AC97

#define ESAI_xCCR_xDC_AC97   SET_BITS(13, 9, 0x0C)

ESAI_xCCR_xDC_MASK

#define ESAI_xCCR_xDC_MASK   MASK(13, 9)

ESAI_xCCR_xFP

#define ESAI_xCCR_xFP

(

div

)

Value:

SET_BITS(17, 14, (div) - 1)

ESAI_xCCR_xFP_MASK

#define ESAI_xCCR_xFP_MASK   MASK(17, 14)

ESAI_xCCR_xFSD

#define ESAI_xCCR_xFSD   BIT(22)

ESAI_xCCR_xFSP

#define ESAI_xCCR_xFSP   BIT(19)

ESAI_xCCR_xHCKD

#define ESAI_xCCR_xHCKD   BIT(23)

ESAI_xCCR_xHCKP

#define ESAI_xCCR_xHCKP   BIT(20)

ESAI_xCCR_xPM

#define ESAI_xCCR_xPM

(

v

)

Value:

SET_BITS(7, 0, (v) - 1)

ESAI_xCCR_xPM_MASK

#define ESAI_xCCR_xPM_MASK   MASK(7, 0)

ESAI_xCCR_xPSR_BYPASS

#define ESAI_xCCR_xPSR_BYPASS   SET_BITS(8, 8, 1)

ESAI_xCCR_xPSR_DIV8

#define ESAI_xCCR_xPSR_DIV8   SET_BITS(8, 8, 0)

ESAI_xCCR_xPSR_MASK

#define ESAI_xCCR_xPSR_MASK   MASK(8, 8)

ESAI_xCR_PADC

#define ESAI_xCR_PADC   BIT(17) /* only valid on tx */

ESAI_xCR_RE

#define ESAI_xCR_RE

(

v

)

Value:

ESAI_xCR_RE_SET(MASK((v) - 1, 0))

ESAI_xCR_RE_MASK

#define ESAI_xCR_RE_MASK   MASK(3, 0)

ESAI_xCR_RE_SET

#define ESAI_xCR_RE_SET

(

v

)

Value:

SET_BITS(3, 0, v)

ESAI_xCR_TE

#define ESAI_xCR_TE

(

v

)

Value:

ESAI_xCR_TE_SET(MASK((v) - 1, 0))

ESAI_xCR_TE_MASK

#define ESAI_xCR_TE_MASK   MASK(5, 0)

ESAI_xCR_TE_SET

#define ESAI_xCR_TE_SET

(

v

)

Value:

SET_BITS(5, 0, v)

ESAI_xCR_xE

#define ESAI_xCR_xE	(		rx,
			v )

Value:

(rx ? ESAI_xCR_RE(v) : ESAI_xCR_TE(v))

ESAI_xCR_xE_MASK

#define ESAI_xCR_xE_MASK

(

rx

)

Value:

(rx ? ESAI_xCR_RE_MASK : ESAI_xCR_TE_MASK)

ESAI_xCR_xEDIE

#define ESAI_xCR_xEDIE   BIT(21)

ESAI_xCR_xEIE

#define ESAI_xCR_xEIE   BIT(20)

ESAI_xCR_xFSL

#define ESAI_xCR_xFSL   BIT(15)

ESAI_xCR_xFSR

#define ESAI_xCR_xFSR   BIT(16)

ESAI_xCR_xIE

#define ESAI_xCR_xIE   BIT(22)

ESAI_xCR_xLIE

#define ESAI_xCR_xLIE   BIT(23)

ESAI_xCR_xMOD_AC97

#define ESAI_xCR_xMOD_AC97   SET_BITS(9, 8, 3)

ESAI_xCR_xMOD_MASK

#define ESAI_xCR_xMOD_MASK   MASK(9, 8)

ESAI_xCR_xMOD_NETWORK

#define ESAI_xCR_xMOD_NETWORK   SET_BITS(9, 8, 1)

ESAI_xCR_xMOD_NORMAL

#define ESAI_xCR_xMOD_NORMAL   SET_BITS(9, 8, 0)

ESAI_xCR_xPR

#define ESAI_xCR_xPR   BIT(19)

ESAI_xCR_xSHFD

#define ESAI_xCR_xSHFD   BIT(6)

ESAI_xCR_xSWS

#define ESAI_xCR_xSWS	(		s,
			w )

Value:

SET_BITS(14, 10, ESAI_xCR_xSWS_VAL(s, w))

ESAI_xCR_xSWS_MASK

#define ESAI_xCR_xSWS_MASK   MASK(14, 10)

ESAI_xCR_xSWS_VAL

#define ESAI_xCR_xSWS_VAL	(		s,
			w )

Value:

                      ((w) < 24 ? ((s) - (w) + (((w) - 8) >> 2)) \
                      : ((s) < 32 ? 0x1e : 0x1f))

ESAI_xCR_xWA

#define ESAI_xCR_xWA   BIT(7)

ESAI_xFCR_RE

#define ESAI_xFCR_RE

(

x

)

Value:

SET_BITS(5, 2, MASK((x) - 1, 0))

ESAI_xFCR_RE_MASK

#define ESAI_xFCR_RE_MASK   MASK(5, 2)

ESAI_xFCR_RE_WIDTH

#define ESAI_xFCR_RE_WIDTH   4

ESAI_xFCR_TE

#define ESAI_xFCR_TE

(

x

)

Value:

SET_BITS(7, 2, MASK((x) - 1, 0))

ESAI_xFCR_TE_MASK

#define ESAI_xFCR_TE_MASK   MASK(7, 2)

ESAI_xFCR_TE_WIDTH

#define ESAI_xFCR_TE_WIDTH   6

ESAI_xFCR_TIEN

#define ESAI_xFCR_TIEN   BIT(19)

ESAI_xFCR_xE

#define ESAI_xFCR_xE	(		rx,
			x )

Value:

(rx ? ESAI_xFCR_RE(x) : ESAI_xFCR_TE(x))

ESAI_xFCR_xE_MASK

#define ESAI_xFCR_xE_MASK

(

rx

)

Value:

(rx ? ESAI_xFCR_RE_MASK : ESAI_xFCR_TE_MASK)

ESAI_xFCR_xE_SHIFT

#define ESAI_xFCR_xE_SHIFT   2

ESAI_xFCR_xFEN

#define ESAI_xFCR_xFEN   BIT(0)

ESAI_xFCR_xFEN_MASK

#define ESAI_xFCR_xFEN_MASK   BIT(0)

ESAI_xFCR_xFEN_SHIFT

#define ESAI_xFCR_xFEN_SHIFT   0

ESAI_xFCR_xFR

#define ESAI_xFCR_xFR   BIT(1)

ESAI_xFCR_xFR_MASK

#define ESAI_xFCR_xFR_MASK   BIT(1)

ESAI_xFCR_xFR_SHIFT

#define ESAI_xFCR_xFR_SHIFT   1

ESAI_xFCR_xFWM

#define ESAI_xFCR_xFWM

(

v

)

Value:

SET_BITS(15, 8, (v) - 1)

ESAI_xFCR_xFWM_MASK

#define ESAI_xFCR_xFWM_MASK   MASK(15, 8)

ESAI_xFCR_xFWM_SHIFT

#define ESAI_xFCR_xFWM_SHIFT   8

ESAI_xFCR_xFWM_WIDTH

#define ESAI_xFCR_xFWM_WIDTH   8

ESAI_xFCR_xWA

#define ESAI_xFCR_xWA

(

v

)

Value:

SET_BITS(18, 16, 8 - ((v) >> 2))

ESAI_xFCR_xWA_MASK

#define ESAI_xFCR_xWA_MASK   MASK(18, 16)

ESAI_xFCR_xWA_SHIFT

#define ESAI_xFCR_xWA_SHIFT   16

ESAI_xFCR_xWA_WIDTH

#define ESAI_xFCR_xWA_WIDTH   3

ESAI_xFSR_NRFI_MASK

#define ESAI_xFSR_NRFI_MASK   MASK(13, 12)

ESAI_xFSR_NRFO_MASK

#define ESAI_xFSR_NRFO_MASK   MASK(9, 8)

ESAI_xFSR_NTFI_MASK

#define ESAI_xFSR_NTFI_MASK   MASK(10, 8)

ESAI_xFSR_NTFO_MASK

#define ESAI_xFSR_NTFO_MASK   MASK(14, 12)

ESAI_xFSR_xFCNT_MASK

#define ESAI_xFSR_xFCNT_MASK   MASK(7, 0)

ESAI_xSMA_xS

#define ESAI_xSMA_xS

(

v

)

Value:

SET_BITS(15, 0, v)

ESAI_xSMA_xS_CHANS

#define ESAI_xSMA_xS_CHANS

(

ch

)

Value:

ESAI_xSMA_xS(MASK((ch) - 1, 0))

ESAI_xSMA_xS_MASK

#define ESAI_xSMA_xS_MASK   MASK(15, 0)

ESAI_xSMB_xS

#define ESAI_xSMB_xS

(

v

)

Value:

SET_BITS(15, 0, (v) >> 16)

ESAI_xSMB_xS_CHANS

#define ESAI_xSMB_xS_CHANS

(

ch

)

Value:

ESAI_xSMB_xS(MASK((ch) - 1, 0))

ESAI_xSMB_xS_MASK

#define ESAI_xSMB_xS_MASK   MASK(15, 0)

REG_ESAI_ECR

#define REG_ESAI_ECR   0x08

REG_ESAI_ERDR

#define REG_ESAI_ERDR   0x04

REG_ESAI_ESR

#define REG_ESAI_ESR   0x0C

REG_ESAI_ETDR

#define REG_ESAI_ETDR   0x00

REG_ESAI_PCRC

#define REG_ESAI_PCRC   0xFC

REG_ESAI_PRRC

#define REG_ESAI_PRRC   0xF8

REG_ESAI_RCCR

#define REG_ESAI_RCCR   0xE0

REG_ESAI_RCR

#define REG_ESAI_RCR   0xDC

REG_ESAI_RFCR

#define REG_ESAI_RFCR   0x18

REG_ESAI_RFSR

#define REG_ESAI_RFSR   0x1C

REG_ESAI_RSMA

#define REG_ESAI_RSMA   0xEC

REG_ESAI_RSMB

#define REG_ESAI_RSMB   0xF0

REG_ESAI_RX0

#define REG_ESAI_RX0   0xA0

REG_ESAI_RX1

#define REG_ESAI_RX1   0xA4

REG_ESAI_RX2

#define REG_ESAI_RX2   0xA8

REG_ESAI_RX3

#define REG_ESAI_RX3   0xAC

REG_ESAI_SAICR

#define REG_ESAI_SAICR   0xD0

REG_ESAI_SAISR

#define REG_ESAI_SAISR   0xCC

REG_ESAI_TCCR

#define REG_ESAI_TCCR   0xD8

REG_ESAI_TCR

#define REG_ESAI_TCR   0xD4

REG_ESAI_TFCR

#define REG_ESAI_TFCR   0x10

REG_ESAI_TFSR

#define REG_ESAI_TFSR   0x14

REG_ESAI_TSMA

#define REG_ESAI_TSMA   0xE4

REG_ESAI_TSMB

#define REG_ESAI_TSMB   0xE8

REG_ESAI_TSR

#define REG_ESAI_TSR   0x98

REG_ESAI_TX0

#define REG_ESAI_TX0   0x80

REG_ESAI_TX1

#define REG_ESAI_TX1   0x84

REG_ESAI_TX2

#define REG_ESAI_TX2   0x88

REG_ESAI_TX3

#define REG_ESAI_TX3   0x8C

REG_ESAI_TX4

#define REG_ESAI_TX4   0x90

REG_ESAI_TX5

#define REG_ESAI_TX5   0x94

REG_ESAI_xCCR

#define REG_ESAI_xCCR

(

rx

)

Value:

(rx ? REG_ESAI_RCCR : REG_ESAI_TCCR)

REG_ESAI_xCR

#define REG_ESAI_xCR

(

rx

)

Value:

(rx ? REG_ESAI_RCR : REG_ESAI_TCR)

REG_ESAI_xFCR

#define REG_ESAI_xFCR

(

rx

)

Value:

(rx ? REG_ESAI_RFCR : REG_ESAI_TFCR)

REG_ESAI_xFSR

#define REG_ESAI_xFSR

(

rx

)

Value:

(rx ? REG_ESAI_RFSR : REG_ESAI_TFSR)

REG_ESAI_xSMA

#define REG_ESAI_xSMA

(

rx

)

Value:

(rx ? REG_ESAI_RSMA : REG_ESAI_TSMA)

REG_ESAI_xSMB

#define REG_ESAI_xSMB

(

rx

)

Value:

(rx ? REG_ESAI_RSMB : REG_ESAI_TSMB)

Variable Documentation

esai_driver

const struct dai_driver esai_driver

extern