micfil.h File Reference

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Data Structures
struct	micfil_pdata

Macros
#define	REG_MICFIL_CTRL1   0x00
#define	REG_MICFIL_CTRL2   0x04
#define	REG_MICFIL_STAT   0x08
#define	REG_MICFIL_FIFO_CTRL   0x10
#define	REG_MICFIL_FIFO_STAT   0x14
#define	REG_MICFIL_DATACH0   0x24
#define	REG_MICFIL_DATACH1   0x28
#define	REG_MICFIL_DATACH2   0x2C
#define	REG_MICFIL_DATACH3   0x30
#define	REG_MICFIL_DATACH4   0x34
#define	REG_MICFIL_DATACH5   0x38
#define	REG_MICFIL_DATACH6   0x3C
#define	REG_MICFIL_DATACH7   0x40
#define	REG_MICFIL_DC_CTRL   0x64
#define	REG_MICFIL_OUT_CTRL   0x74
#define	REG_MICFIL_OUT_STAT   0x7C
#define	REG_MICFIL_VAD0_CTRL1   0x90
#define	REG_MICFIL_VAD0_CTRL2   0x94
#define	REG_MICFIL_VAD0_STAT   0x98
#define	REG_MICFIL_VAD0_SCONFIG   0x9C
#define	REG_MICFIL_VAD0_NCONFIG   0xA0
#define	REG_MICFIL_VAD0_NDATA   0xA4
#define	REG_MICFIL_VAD0_ZCD   0xA8
#define	MICFIL_CTRL1_MDIS   BIT(31)
#define	MICFIL_CTRL1_DOZEN   BIT(30)
#define	MICFIL_CTRL1_PDMIEN   BIT(29)
#define	MICFIL_CTRL1_DBG   BIT(28)
#define	MICFIL_CTRL1_SRES   BIT(27)
#define	MICFIL_CTRL1_DBGE   BIT(26)
#define	MICFIL_CTRL1_CHNEN   MASK(7, 0)
#define	MICFIL_CTRL1_DISEL_DISABLE   0
#define	MICFIL_CTRL1_DISEL_DMA   1
#define	MICFIL_CTRL1_DISEL_IRQ   2
#define	MICFIL_CTRL1_DISEL_BITS(x)
#define	MICFIL_CTRL1_DISEL   MASK(25, 24)
#define	MICFIL_CTRL1_ERREN   BIT(23)
#define	MICFIL_CTRL1_CHEN(ch)
#define	MICFIL_CTRL2_QSEL_SHIFT   25
#define	MICFIL_CTRL2_QSEL   MASK(27, 25)
#define	MICFIL_CTRL2_QSEL_BITS(x)
#define	MICFIL_QSEL_MEDIUM_QUALITY   0
#define	MICFIL_QSEL_HIGH_QUALITY   1
#define	MICFIL_QSEL_LOW_QUALITY   7
#define	MICFIL_QSEL_VLOW0_QUALITY   6
#define	MICFIL_QSEL_VLOW1_QUALITY   5
#define	MICFIL_QSEL_VLOW2_QUALITY   4
#define	MICFIL_CTRL2_CICOSR   MASK(19, 16)
#define	MICFIL_CTRL2_CICOSR_SHIFT   16
#define	MICFIL_CTRL2_CICOSR_BITS(x)
#define	MICFIL_CTRL2_CLKDIV   MASK(7, 0)
#define	MICFIL_CTRL2_CLKDIV_BITS(x)
#define	MICFIL_STAT_BSY_FIL   BIT(31)
#define	MICFIL_STAT_FIR_RDY   BIT(30)
#define	MICFIL_STAT_LOWFREQF   BIT(29)
#define	MICFIL_STAT_CHXF(ch)
#define	MICFIL_FIFO_CTRL_FIFOWMK   MASK(2, 0)
#define	MICFIL_FIFO_CTRL_FIFOWMK_BITS(x)
#define	MICFIL_FIFO_STAT_FIFOX_OVER(ch)
#define	MICFIL_FIFO_STAT_FIFOX_UNDER(ch)
#define	MICFIL_DC_CTRL_CONFIG   MASK(15, 0)
#define	MICFIL_DC_CHX_SHIFT(ch)
#define	MICFIL_DC_CHX(ch)
#define	MICFIL_DC_CUTOFF_21HZ   0
#define	MICFIL_DC_CUTOFF_83HZ   1
#define	MICFIL_DC_CUTOFF_152Hz   2
#define	MICFIL_DC_BYPASS   3
#define	MICFIL_VAD0_CTRL1_CHSEL   MASK(26, 24)
#define	MICFIL_VAD0_CTRL1_CICOSR   MASK(19, 16)
#define	MICFIL_VAD0_CTRL1_INITT   MASK(12, 8)
#define	MICFIL_VAD0_CTRL1_ST10   BIT(4)
#define	MICFIL_VAD0_CTRL1_ERIE   BIT(3)
#define	MICFIL_VAD0_CTRL1_IE   BIT(2)
#define	MICFIL_VAD0_CTRL1_RST   BIT(1)
#define	MICFIL_VAD0_CTRL1_EN   BIT(0)
#define	MICFIL_VAD0_CTRL2_FRENDIS   BIT(31)
#define	MICFIL_VAD0_CTRL2_PREFEN   BIT(30)
#define	MICFIL_VAD0_CTRL2_FOUTDIS   BIT(28)
#define	MICFIL_VAD0_CTRL2_FRAMET   MASK(21, 16)
#define	MICFIL_VAD0_CTRL2_INPGAIN   MASK(11, 8)
#define	MICFIL_VAD0_CTRL2_HPF   MASK(1, 0)
#define	MICFIL_VAD0_SCONFIG_SFILEN   BIT(31)
#define	MICFIL_VAD0_SCONFIG_SMAXEN   BIT(30)
#define	MICFIL_VAD0_SCONFIG_SGAIN   MASK(3, 0)
#define	MICFIL_VAD0_NCONFIG_NFILAUT   BIT(31)
#define	MICFIL_VAD0_NCONFIG_NMINEN   BIT(30)
#define	MICFIL_VAD0_NCONFIG_NDECEN   BIT(29)
#define	MICFIL_VAD0_NCONFIG_NOREN   BIT(28)
#define	MICFIL_VAD0_NCONFIG_NFILADJ   MASK(12, 8)
#define	MICFIL_VAD0_NCONFIG_NGAIN   MASK(3, 0)
#define	MICFIL_VAD0_ZCD_ZCDTH   MASK(25, 16)
#define	MICFIL_VAD0_ZCD_ZCDADJ   MASK(11, 8)
#define	MICFIL_VAD0_ZCD_ZCDAND   BIT(4)
#define	MICFIL_VAD0_ZCD_ZCDAUT   BIT(2)
#define	MICFIL_VAD0_ZCD_ZCDEN   BIT(0)
#define	MICFIL_VAD0_STAT_INITF   BIT(31)
#define	MICFIL_VAD0_STAT_INSATF   BIT(16)
#define	MICFIL_VAD0_STAT_EF   BIT(15)
#define	MICFIL_VAD0_STAT_IF   BIT(0)
#define	MICFIL_OUTGAIN_CHX_SHIFT(v)
#define	MICFIL_OUTPUT_CHANNELS   8
#define	MICFIL_FIFO_NUM   8
#define	FIFO_PTRWID   3
#define	FIFO_LEN   BIT(FIFO_PTRWID)
#define	MICFIL_IRQ_LINES   4
#define	MICFIL_MAX_RETRY   25
#define	MICFIL_SLEEP_MIN   90000 /* in us */
#define	MICFIL_SLEEP_MAX   100000 /* in us */
#define	MICFIL_DMA_MAXBURST_RX   6
#define	MICFIL_HWVAD_ENVELOPE_MODE   0
#define	MICFIL_HWVAD_ENERGY_MODE   1

Variables
const struct dai_driver	micfil_driver

Macro Definition Documentation

FIFO_LEN

#define FIFO_LEN   BIT(FIFO_PTRWID)

FIFO_PTRWID

#define FIFO_PTRWID   3

MICFIL_CTRL1_CHEN

#define MICFIL_CTRL1_CHEN

(

ch

)

Value:

BIT(ch)

MICFIL_CTRL1_CHNEN

#define MICFIL_CTRL1_CHNEN   MASK(7, 0)

MICFIL_CTRL1_DBG

#define MICFIL_CTRL1_DBG   BIT(28)

MICFIL_CTRL1_DBGE

#define MICFIL_CTRL1_DBGE   BIT(26)

MICFIL_CTRL1_DISEL

#define MICFIL_CTRL1_DISEL   MASK(25, 24)

MICFIL_CTRL1_DISEL_BITS

#define MICFIL_CTRL1_DISEL_BITS

(

x

)

Value:

SET_BITS(25, 24, x)

MICFIL_CTRL1_DISEL_DISABLE

#define MICFIL_CTRL1_DISEL_DISABLE   0

MICFIL_CTRL1_DISEL_DMA

#define MICFIL_CTRL1_DISEL_DMA   1

MICFIL_CTRL1_DISEL_IRQ

#define MICFIL_CTRL1_DISEL_IRQ   2

MICFIL_CTRL1_DOZEN

#define MICFIL_CTRL1_DOZEN   BIT(30)

MICFIL_CTRL1_ERREN

#define MICFIL_CTRL1_ERREN   BIT(23)

MICFIL_CTRL1_MDIS

#define MICFIL_CTRL1_MDIS   BIT(31)

MICFIL_CTRL1_PDMIEN

#define MICFIL_CTRL1_PDMIEN   BIT(29)

MICFIL_CTRL1_SRES

#define MICFIL_CTRL1_SRES   BIT(27)

MICFIL_CTRL2_CICOSR

#define MICFIL_CTRL2_CICOSR   MASK(19, 16)

MICFIL_CTRL2_CICOSR_BITS

#define MICFIL_CTRL2_CICOSR_BITS

(

x

)

Value:

SET_BITS(19, 16, x)

MICFIL_CTRL2_CICOSR_SHIFT

#define MICFIL_CTRL2_CICOSR_SHIFT   16

MICFIL_CTRL2_CLKDIV

#define MICFIL_CTRL2_CLKDIV   MASK(7, 0)

MICFIL_CTRL2_CLKDIV_BITS

#define MICFIL_CTRL2_CLKDIV_BITS

(

x

)

Value:

SET_BITS(7, 0, x)

MICFIL_CTRL2_QSEL

#define MICFIL_CTRL2_QSEL   MASK(27, 25)

MICFIL_CTRL2_QSEL_BITS

#define MICFIL_CTRL2_QSEL_BITS

(

x

)

Value:

SET_BITS(27, 25, x)

MICFIL_CTRL2_QSEL_SHIFT

#define MICFIL_CTRL2_QSEL_SHIFT   25

MICFIL_DC_BYPASS

#define MICFIL_DC_BYPASS   3

MICFIL_DC_CHX

#define MICFIL_DC_CHX

(

ch

)

Value:

MASK((((ch) << 1) + 1), ((ch) << 1))

MICFIL_DC_CHX_SHIFT

#define MICFIL_DC_CHX_SHIFT

(

ch

)

Value:

((ch) << 1)

MICFIL_DC_CTRL_CONFIG

#define MICFIL_DC_CTRL_CONFIG   MASK(15, 0)

MICFIL_DC_CUTOFF_152Hz

#define MICFIL_DC_CUTOFF_152Hz   2

MICFIL_DC_CUTOFF_21HZ

#define MICFIL_DC_CUTOFF_21HZ   0

MICFIL_DC_CUTOFF_83HZ

#define MICFIL_DC_CUTOFF_83HZ   1

MICFIL_DMA_MAXBURST_RX

#define MICFIL_DMA_MAXBURST_RX   6

MICFIL_FIFO_CTRL_FIFOWMK

#define MICFIL_FIFO_CTRL_FIFOWMK   MASK(2, 0)

MICFIL_FIFO_CTRL_FIFOWMK_BITS

#define MICFIL_FIFO_CTRL_FIFOWMK_BITS

(

x

)

Value:

SET_BITS(2, 0, x)

MICFIL_FIFO_NUM

#define MICFIL_FIFO_NUM   8

MICFIL_FIFO_STAT_FIFOX_OVER

#define MICFIL_FIFO_STAT_FIFOX_OVER

(

ch

)

Value:

BIT(ch)

MICFIL_FIFO_STAT_FIFOX_UNDER

#define MICFIL_FIFO_STAT_FIFOX_UNDER

(

ch

)

Value:

BIT((ch) + 8)

MICFIL_HWVAD_ENERGY_MODE

#define MICFIL_HWVAD_ENERGY_MODE   1

MICFIL_HWVAD_ENVELOPE_MODE

#define MICFIL_HWVAD_ENVELOPE_MODE   0

MICFIL_IRQ_LINES

#define MICFIL_IRQ_LINES   4

MICFIL_MAX_RETRY

#define MICFIL_MAX_RETRY   25

MICFIL_OUTGAIN_CHX_SHIFT

#define MICFIL_OUTGAIN_CHX_SHIFT

(

v

)

Value:

(4 * (v))

MICFIL_OUTPUT_CHANNELS

#define MICFIL_OUTPUT_CHANNELS   8

MICFIL_QSEL_HIGH_QUALITY

#define MICFIL_QSEL_HIGH_QUALITY   1

MICFIL_QSEL_LOW_QUALITY

#define MICFIL_QSEL_LOW_QUALITY   7

MICFIL_QSEL_MEDIUM_QUALITY

#define MICFIL_QSEL_MEDIUM_QUALITY   0

MICFIL_QSEL_VLOW0_QUALITY

#define MICFIL_QSEL_VLOW0_QUALITY   6

MICFIL_QSEL_VLOW1_QUALITY

#define MICFIL_QSEL_VLOW1_QUALITY   5

MICFIL_QSEL_VLOW2_QUALITY

#define MICFIL_QSEL_VLOW2_QUALITY   4

MICFIL_SLEEP_MAX

#define MICFIL_SLEEP_MAX   100000 /* in us */

MICFIL_SLEEP_MIN

#define MICFIL_SLEEP_MIN   90000 /* in us */

MICFIL_STAT_BSY_FIL

#define MICFIL_STAT_BSY_FIL   BIT(31)

MICFIL_STAT_CHXF

#define MICFIL_STAT_CHXF

(

ch

)

Value:

BIT(ch)

MICFIL_STAT_FIR_RDY

#define MICFIL_STAT_FIR_RDY   BIT(30)

MICFIL_STAT_LOWFREQF

#define MICFIL_STAT_LOWFREQF   BIT(29)

MICFIL_VAD0_CTRL1_CHSEL

#define MICFIL_VAD0_CTRL1_CHSEL   MASK(26, 24)

MICFIL_VAD0_CTRL1_CICOSR

#define MICFIL_VAD0_CTRL1_CICOSR   MASK(19, 16)

MICFIL_VAD0_CTRL1_EN

#define MICFIL_VAD0_CTRL1_EN   BIT(0)

MICFIL_VAD0_CTRL1_ERIE

#define MICFIL_VAD0_CTRL1_ERIE   BIT(3)

MICFIL_VAD0_CTRL1_IE

#define MICFIL_VAD0_CTRL1_IE   BIT(2)

MICFIL_VAD0_CTRL1_INITT

#define MICFIL_VAD0_CTRL1_INITT   MASK(12, 8)

MICFIL_VAD0_CTRL1_RST

#define MICFIL_VAD0_CTRL1_RST   BIT(1)

MICFIL_VAD0_CTRL1_ST10

#define MICFIL_VAD0_CTRL1_ST10   BIT(4)

MICFIL_VAD0_CTRL2_FOUTDIS

#define MICFIL_VAD0_CTRL2_FOUTDIS   BIT(28)

MICFIL_VAD0_CTRL2_FRAMET

#define MICFIL_VAD0_CTRL2_FRAMET   MASK(21, 16)

MICFIL_VAD0_CTRL2_FRENDIS

#define MICFIL_VAD0_CTRL2_FRENDIS   BIT(31)

MICFIL_VAD0_CTRL2_HPF

#define MICFIL_VAD0_CTRL2_HPF   MASK(1, 0)

MICFIL_VAD0_CTRL2_INPGAIN

#define MICFIL_VAD0_CTRL2_INPGAIN   MASK(11, 8)

MICFIL_VAD0_CTRL2_PREFEN

#define MICFIL_VAD0_CTRL2_PREFEN   BIT(30)

MICFIL_VAD0_NCONFIG_NDECEN

#define MICFIL_VAD0_NCONFIG_NDECEN   BIT(29)

MICFIL_VAD0_NCONFIG_NFILADJ

#define MICFIL_VAD0_NCONFIG_NFILADJ   MASK(12, 8)

MICFIL_VAD0_NCONFIG_NFILAUT

#define MICFIL_VAD0_NCONFIG_NFILAUT   BIT(31)

MICFIL_VAD0_NCONFIG_NGAIN

#define MICFIL_VAD0_NCONFIG_NGAIN   MASK(3, 0)

MICFIL_VAD0_NCONFIG_NMINEN

#define MICFIL_VAD0_NCONFIG_NMINEN   BIT(30)

MICFIL_VAD0_NCONFIG_NOREN

#define MICFIL_VAD0_NCONFIG_NOREN   BIT(28)

MICFIL_VAD0_SCONFIG_SFILEN

#define MICFIL_VAD0_SCONFIG_SFILEN   BIT(31)

MICFIL_VAD0_SCONFIG_SGAIN

#define MICFIL_VAD0_SCONFIG_SGAIN   MASK(3, 0)

MICFIL_VAD0_SCONFIG_SMAXEN

#define MICFIL_VAD0_SCONFIG_SMAXEN   BIT(30)

MICFIL_VAD0_STAT_EF

#define MICFIL_VAD0_STAT_EF   BIT(15)

MICFIL_VAD0_STAT_IF

#define MICFIL_VAD0_STAT_IF   BIT(0)

MICFIL_VAD0_STAT_INITF

#define MICFIL_VAD0_STAT_INITF   BIT(31)

MICFIL_VAD0_STAT_INSATF

#define MICFIL_VAD0_STAT_INSATF   BIT(16)

MICFIL_VAD0_ZCD_ZCDADJ

#define MICFIL_VAD0_ZCD_ZCDADJ   MASK(11, 8)

MICFIL_VAD0_ZCD_ZCDAND

#define MICFIL_VAD0_ZCD_ZCDAND   BIT(4)

MICFIL_VAD0_ZCD_ZCDAUT

#define MICFIL_VAD0_ZCD_ZCDAUT   BIT(2)

MICFIL_VAD0_ZCD_ZCDEN

#define MICFIL_VAD0_ZCD_ZCDEN   BIT(0)

MICFIL_VAD0_ZCD_ZCDTH

#define MICFIL_VAD0_ZCD_ZCDTH   MASK(25, 16)

REG_MICFIL_CTRL1

#define REG_MICFIL_CTRL1   0x00

REG_MICFIL_CTRL2

#define REG_MICFIL_CTRL2   0x04

REG_MICFIL_DATACH0

#define REG_MICFIL_DATACH0   0x24

REG_MICFIL_DATACH1

#define REG_MICFIL_DATACH1   0x28

REG_MICFIL_DATACH2

#define REG_MICFIL_DATACH2   0x2C

REG_MICFIL_DATACH3

#define REG_MICFIL_DATACH3   0x30

REG_MICFIL_DATACH4

#define REG_MICFIL_DATACH4   0x34

REG_MICFIL_DATACH5

#define REG_MICFIL_DATACH5   0x38

REG_MICFIL_DATACH6

#define REG_MICFIL_DATACH6   0x3C

REG_MICFIL_DATACH7

#define REG_MICFIL_DATACH7   0x40

REG_MICFIL_DC_CTRL

#define REG_MICFIL_DC_CTRL   0x64

REG_MICFIL_FIFO_CTRL

#define REG_MICFIL_FIFO_CTRL   0x10

REG_MICFIL_FIFO_STAT

#define REG_MICFIL_FIFO_STAT   0x14

REG_MICFIL_OUT_CTRL

#define REG_MICFIL_OUT_CTRL   0x74

REG_MICFIL_OUT_STAT

#define REG_MICFIL_OUT_STAT   0x7C

REG_MICFIL_STAT

#define REG_MICFIL_STAT   0x08

REG_MICFIL_VAD0_CTRL1

#define REG_MICFIL_VAD0_CTRL1   0x90

REG_MICFIL_VAD0_CTRL2

#define REG_MICFIL_VAD0_CTRL2   0x94

REG_MICFIL_VAD0_NCONFIG

#define REG_MICFIL_VAD0_NCONFIG   0xA0

REG_MICFIL_VAD0_NDATA

#define REG_MICFIL_VAD0_NDATA   0xA4

REG_MICFIL_VAD0_SCONFIG

#define REG_MICFIL_VAD0_SCONFIG   0x9C

REG_MICFIL_VAD0_STAT

#define REG_MICFIL_VAD0_STAT   0x98

REG_MICFIL_VAD0_ZCD

#define REG_MICFIL_VAD0_ZCD   0xA8

Variable Documentation

micfil_driver

const struct dai_driver micfil_driver

extern