sai.h File Reference

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Data Structures
struct	sai_pdata

Macros
#define	SAI_OFS   0
#define	REG_SAI_FORMATS
#define	REG_SAI_VERID   0x00 /* SAI Version ID Register */
#define	REG_SAI_PARAM   0x04 /* SAI Parameter Register */
#define	REG_SAI_TCSR   (0x00 + SAI_OFS) /* SAI Transmit Control */
#define	REG_SAI_TCR1   (0x04 + SAI_OFS) /* SAI Transmit Configuration 1 */
#define	REG_SAI_TCR2   (0x08 + SAI_OFS) /* SAI Transmit Configuration 2 */
#define	REG_SAI_TCR3   (0x0c + SAI_OFS) /* SAI Transmit Configuration 3 */
#define	REG_SAI_TCR4   (0x10 + SAI_OFS) /* SAI Transmit Configuration 4 */
#define	REG_SAI_TCR5   (0x14 + SAI_OFS) /* SAI Transmit Configuration 5 */
#define	REG_SAI_TDR0   0x20 /* SAI Transmit Data */
#define	REG_SAI_TDR1   0x24 /* SAI Transmit Data */
#define	REG_SAI_TDR2   0x28 /* SAI Transmit Data */
#define	REG_SAI_TDR3   0x2C /* SAI Transmit Data */
#define	REG_SAI_TDR4   0x30 /* SAI Transmit Data */
#define	REG_SAI_TDR5   0x34 /* SAI Transmit Data */
#define	REG_SAI_TDR6   0x38 /* SAI Transmit Data */
#define	REG_SAI_TDR7   0x3C /* SAI Transmit Data */
#define	REG_SAI_TFR0   0x40 /* SAI Transmit FIFO */
#define	REG_SAI_TFR1   0x44 /* SAI Transmit FIFO */
#define	REG_SAI_TFR2   0x48 /* SAI Transmit FIFO */
#define	REG_SAI_TFR3   0x4C /* SAI Transmit FIFO */
#define	REG_SAI_TFR4   0x50 /* SAI Transmit FIFO */
#define	REG_SAI_TFR5   0x54 /* SAI Transmit FIFO */
#define	REG_SAI_TFR6   0x58 /* SAI Transmit FIFO */
#define	REG_SAI_TFR7   0x5C /* SAI Transmit FIFO */
#define	REG_SAI_TMR   0x60 /* SAI Transmit Mask */
#define	REG_SAI_TTCTL   0x70 /* SAI Transmit Timestamp Control Register */
#define	REG_SAI_TTCTN   0x74 /* SAI Transmit Timestamp Counter Register */
#define	REG_SAI_TBCTN   0x78 /* SAI Transmit Bit Counter Register */
#define	REG_SAI_TTCAP   0x7C /* SAI Transmit Timestamp Capture */
#define	REG_SAI_RCSR   (0x80 + SAI_OFS) /* SAI Receive Control */
#define	REG_SAI_RCR1   (0x84 + SAI_OFS) /* SAI Receive Configuration 1 */
#define	REG_SAI_RCR2   (0x88 + SAI_OFS) /* SAI Receive Configuration 2 */
#define	REG_SAI_RCR3   (0x8c + SAI_OFS) /* SAI Receive Configuration 3 */
#define	REG_SAI_RCR4   (0x90 + SAI_OFS) /* SAI Receive Configuration 4 */
#define	REG_SAI_RCR5   (0x94 + SAI_OFS) /* SAI Receive Configuration 5 */
#define	REG_SAI_RDR0   0xa0 /* SAI Receive Data */
#define	REG_SAI_RDR1   0xa4 /* SAI Receive Data */
#define	REG_SAI_RDR2   0xa8 /* SAI Receive Data */
#define	REG_SAI_RDR3   0xac /* SAI Receive Data */
#define	REG_SAI_RDR4   0xb0 /* SAI Receive Data */
#define	REG_SAI_RDR5   0xb4 /* SAI Receive Data */
#define	REG_SAI_RDR6   0xb8 /* SAI Receive Data */
#define	REG_SAI_RDR7   0xbc /* SAI Receive Data */
#define	REG_SAI_RFR0   0xc0 /* SAI Receive FIFO */
#define	REG_SAI_RFR1   0xc4 /* SAI Receive FIFO */
#define	REG_SAI_RFR2   0xc8 /* SAI Receive FIFO */
#define	REG_SAI_RFR3   0xcc /* SAI Receive FIFO */
#define	REG_SAI_RFR4   0xd0 /* SAI Receive FIFO */
#define	REG_SAI_RFR5   0xd4 /* SAI Receive FIFO */
#define	REG_SAI_RFR6   0xd8 /* SAI Receive FIFO */
#define	REG_SAI_RFR7   0xdc /* SAI Receive FIFO */
#define	REG_SAI_RMR   0xe0 /* SAI Receive Mask */
#define	REG_SAI_RTCTL   0xf0 /* SAI Receive Timestamp Control Register */
#define	REG_SAI_RTCTN   0xf4 /* SAI Receive Timestamp Counter Register */
#define	REG_SAI_RBCTN   0xf8 /* SAI Receive Bit Counter Register */
#define	REG_SAI_RTCAP   0xfc /* SAI Receive Timestamp Capture */
#define	REG_SAI_MCTL   0x100 /* SAI MCLK Control Register */
#define	REG_SAI_MDIV   0x104 /* SAI MCLK Divide Register */
#define	REG_SAI_XCSR(rx)
#define	REG_SAI_XCR1(rx)
#define	REG_SAI_XCR2(rx)
#define	REG_SAI_XCR3(rx)
#define	REG_SAI_XCR4(rx)
#define	REG_SAI_XCR5(rx)
#define	REG_SAI_XMR(rx)
#define	REG_SAI_XMR_MASK   0xffffffff
#define	REG_SAI_CSR_TERE   BIT(31)
#define	REG_SAI_CSR_SE   BIT(30)
#define	REG_SAI_CSR_FR   BIT(25)
#define	REG_SAI_CSR_SR   BIT(24)
#define	REG_SAI_CSR_XF_SHIFT   16
#define	REG_SAI_CSR_XF_W_SHIFT   18
#define	REG_SAI_CSR_XF_MASK
#define	REG_SAI_CSR_XF_W_MASK
#define	REG_SAI_CSR_WSF   BIT(20)
#define	REG_SAI_CSR_SEF   BIT(19)
#define	REG_SAI_CSR_FEF   BIT(18)
#define	REG_SAI_CSR_FWF   BIT(17)
#define	REG_SAI_CSR_FRF   BIT(16)
#define	REG_SAI_CSR_XIE_SHIFT   8
#define	REG_SAI_CSR_XIE_MASK
#define	REG_SAI_CSR_WSIE   BIT(12)
#define	REG_SAI_CSR_SEIE   BIT(11)
#define	REG_SAI_CSR_FEIE   BIT(10)
#define	REG_SAI_CSR_FWIE   BIT(9)
#define	REG_SAI_CSR_FRIE   BIT(8)
#define	REG_SAI_CSR_FWDE   BIT(1)
#define	REG_SAI_CSR_FRDE   BIT(0)
#define	REG_SAI_CR1_RFW_MASK   0x3f
#define	REG_SAI_CR2_SYNC   SET_BITS(31, 30, 1)
#define	REG_SAI_CR2_SYNC_MASK   MASK(31, 30)
#define	REG_SAI_CR2_MSEL_MASK   MASK(27, 26)
#define	REG_SAI_CR2_MSEL_BUS   SET_BITS(27, 26, 0)
#define	REG_SAI_CR2_MSEL_MCLK1   SET_BITS(27, 26, 1)
#define	REG_SAI_CR2_MSEL_MCLK2   SET_BITS(27, 26, 2)
#define	REG_SAI_CR2_MSEL_MCLK3   SET_BITS(27, 26, 3)
#define	REG_SAI_CR2_MSEL(id)
#define	REG_SAI_CR2_BCP   BIT(25)
#define	REG_SAI_CR2_BCD_MSTR   BIT(24)
#define	REG_SAI_CR2_BYP   BIT(23) /* BCLK bypass */
#define	REG_SAI_CR2_BYP_MASK   BIT(23)
#define	REG_SAI_CR2_DIV_MASK   0xff
#define	REG_SAI_CR3_TRCE_MASK   MASK(23, 16)
#define	REG_SAI_CR3_TRCE(x)
#define	REG_SAI_CR3_WDFL(x)
#define	REG_SAI_CR3_WDFL_MASK   0x1f
#define	REG_SAI_CR4_FCONT   BIT(28)
#define	REG_SAI_CR4_FCOMB_SHIFT   BIT(26)
#define	REG_SAI_CR4_FCOMB_SOFT   BIT(27)
#define	REG_SAI_CR4_FCOMB_MASK   MASK(27, 26)
#define	REG_SAI_CR4_FPACK_8   (0x2 << 24)
#define	REG_SAI_CR4_FPACK_16   (0x3 << 24)
#define	REG_SAI_CR4_FPACK_MASK   MASK(25, 24)
#define	REG_SAI_CR4_FRSZ(x)
#define	REG_SAI_CR4_FRSZ_MASK   MASK(20, 16)
#define	REG_SAI_CR4_SYWD(x)
#define	REG_SAI_CR4_SYWD_MASK   MASK(12, 8)
#define	REG_SAI_CR4_CHMOD   BIT(5)
#define	REG_SAI_CR4_CHMOD_MASK   BIT(5)
#define	REG_SAI_CR4_MF   BIT(4)
#define	REG_SAI_CR4_FSE   BIT(3)
#define	REG_SAI_CR4_FSP   BIT(1)
#define	REG_SAI_CR4_FSD_MSTR   BIT(0)
#define	REG_SAI_CR5_WNW(x)
#define	REG_SAI_CR5_WNW_MASK   MASK(28, 24)
#define	REG_SAI_CR5_W0W(x)
#define	REG_SAI_CR5_W0W_MASK   MASK(20, 16)
#define	REG_SAI_CR5_FBT(x)
#define	REG_SAI_CR5_FBT_MASK   MASK(12, 8)
#define	REG_SAI_MCTL_MCLK_EN   BIT(30) /* MCLK Enable */
#define	REG_SAI_MCTL_MSEL_MASK   MASK(25, 24)
#define	REG_SAI_MCTL_MSEL(id)
#define	REG_SAI_MCTL_MSEL_BUS   SET_BITS(25, 24, 0)
#define	REG_SAI_MCTL_MSEL_MCLK1   SET_BITS(25, 24, 1)
#define	REG_SAI_MCTL_MSEL_MCLK2   SET_BITS(25, 24, 2)
#define	REG_SAI_MCTL_MSEL_MCLK3   SET_BITS(25, 24, 3)
#define	REG_SAI_MCTL_DIV_EN   BIT(23)
#define	REG_SAI_MCTL_DIV_MASK   0xFF
#define	REG_SAI_VER_ID_SHIFT   16
#define	REG_SAI_VER_ID_MASK
#define	REG_SAI_VER_EFIFO_EN   BIT(0)
#define	REG_SAI_VER_TSTMP_EN   BIT(1)
#define	REG_SAI_PAR_SPF_SHIFT   16
#define	REG_SAI_PAR_SPF_MASK
#define	REG_SAI_PAR_WPF_SHIFT   8
#define	REG_SAI_PAR_WPF_MASK
#define	REG_SAI_PAR_DLN_MASK   (0x0F)
#define	REG_SAI_MDIV_MASK   0xFFFFF
#define	REG_SAI_DMA   BIT(0)
#define	REG_SAI_USE_AC97   BIT(1)
#define	REG_SAI_NET   BIT(2)
#define	REG_SAI_TRA_SYN   BIT(3)
#define	REG_SAI_REC_SYN   BIT(4)
#define	REG_SAI_USE_I2S_SLAVE   BIT(5)
#define	REG_FMT_TRANSMITTER   0
#define	REG_FMT_RECEIVER   1
#define	REG_SAI_CLK_BUS   0
#define	REG_SAI_CLK_MAST1   1
#define	REG_SAI_CLK_MAST2   2
#define	REG_SAI_CLK_MAST3   3
#define	REG_SAI_MCLK_MAX   4
#define	REG_SAI_MAXBURST_TX   6
#define	REG_SAI_MAXBURST_RX   6
#define	SAI_FLAG_PMQOS   BIT(0)
#define	SAI_FIFO_WORD_SIZE   64

Variables
const struct dai_driver	sai_driver

Macro Definition Documentation

REG_FMT_RECEIVER

#define REG_FMT_RECEIVER   1

REG_FMT_TRANSMITTER

#define REG_FMT_TRANSMITTER   0

REG_SAI_CLK_BUS

#define REG_SAI_CLK_BUS   0

REG_SAI_CLK_MAST1

#define REG_SAI_CLK_MAST1   1

REG_SAI_CLK_MAST2

#define REG_SAI_CLK_MAST2   2

REG_SAI_CLK_MAST3

#define REG_SAI_CLK_MAST3   3

REG_SAI_CR1_RFW_MASK

#define REG_SAI_CR1_RFW_MASK   0x3f

REG_SAI_CR2_BCD_MSTR

#define REG_SAI_CR2_BCD_MSTR   BIT(24)

REG_SAI_CR2_BCP

#define REG_SAI_CR2_BCP   BIT(25)

REG_SAI_CR2_BYP

#define REG_SAI_CR2_BYP   BIT(23) /* BCLK bypass */

REG_SAI_CR2_BYP_MASK

#define REG_SAI_CR2_BYP_MASK   BIT(23)

REG_SAI_CR2_DIV_MASK

#define REG_SAI_CR2_DIV_MASK   0xff

REG_SAI_CR2_MSEL

#define REG_SAI_CR2_MSEL

(

id

)

Value:

((id) << 26)

REG_SAI_CR2_MSEL_BUS

#define REG_SAI_CR2_MSEL_BUS   SET_BITS(27, 26, 0)

REG_SAI_CR2_MSEL_MASK

#define REG_SAI_CR2_MSEL_MASK   MASK(27, 26)

REG_SAI_CR2_MSEL_MCLK1

#define REG_SAI_CR2_MSEL_MCLK1   SET_BITS(27, 26, 1)

REG_SAI_CR2_MSEL_MCLK2

#define REG_SAI_CR2_MSEL_MCLK2   SET_BITS(27, 26, 2)

REG_SAI_CR2_MSEL_MCLK3

#define REG_SAI_CR2_MSEL_MCLK3   SET_BITS(27, 26, 3)

REG_SAI_CR2_SYNC

#define REG_SAI_CR2_SYNC   SET_BITS(31, 30, 1)

REG_SAI_CR2_SYNC_MASK

#define REG_SAI_CR2_SYNC_MASK   MASK(31, 30)

REG_SAI_CR3_TRCE

#define REG_SAI_CR3_TRCE

(

x

)

Value:

(x << 16)

REG_SAI_CR3_TRCE_MASK

#define REG_SAI_CR3_TRCE_MASK   MASK(23, 16)

REG_SAI_CR3_WDFL

#define REG_SAI_CR3_WDFL

(

x

)

Value:

(x)

REG_SAI_CR3_WDFL_MASK

#define REG_SAI_CR3_WDFL_MASK   0x1f

REG_SAI_CR4_CHMOD

#define REG_SAI_CR4_CHMOD   BIT(5)

REG_SAI_CR4_CHMOD_MASK

#define REG_SAI_CR4_CHMOD_MASK   BIT(5)

REG_SAI_CR4_FCOMB_MASK

#define REG_SAI_CR4_FCOMB_MASK   MASK(27, 26)

REG_SAI_CR4_FCOMB_SHIFT

#define REG_SAI_CR4_FCOMB_SHIFT   BIT(26)

REG_SAI_CR4_FCOMB_SOFT

#define REG_SAI_CR4_FCOMB_SOFT   BIT(27)

REG_SAI_CR4_FCONT

#define REG_SAI_CR4_FCONT   BIT(28)

REG_SAI_CR4_FPACK_16

#define REG_SAI_CR4_FPACK_16   (0x3 << 24)

REG_SAI_CR4_FPACK_8

#define REG_SAI_CR4_FPACK_8   (0x2 << 24)

REG_SAI_CR4_FPACK_MASK

#define REG_SAI_CR4_FPACK_MASK   MASK(25, 24)

REG_SAI_CR4_FRSZ

#define REG_SAI_CR4_FRSZ

(

x

)

Value:

(((x) - 1) << 16)

REG_SAI_CR4_FRSZ_MASK

#define REG_SAI_CR4_FRSZ_MASK   MASK(20, 16)

REG_SAI_CR4_FSD_MSTR

#define REG_SAI_CR4_FSD_MSTR   BIT(0)

REG_SAI_CR4_FSE

#define REG_SAI_CR4_FSE   BIT(3)

REG_SAI_CR4_FSP

#define REG_SAI_CR4_FSP   BIT(1)

REG_SAI_CR4_MF

#define REG_SAI_CR4_MF   BIT(4)

REG_SAI_CR4_SYWD

#define REG_SAI_CR4_SYWD

(

x

)

Value:

(((x) - 1) << 8)

REG_SAI_CR4_SYWD_MASK

#define REG_SAI_CR4_SYWD_MASK   MASK(12, 8)

REG_SAI_CR5_FBT

#define REG_SAI_CR5_FBT

(

x

)

Value:

(((x) - 1) << 8)

REG_SAI_CR5_FBT_MASK

#define REG_SAI_CR5_FBT_MASK   MASK(12, 8)

REG_SAI_CR5_W0W

#define REG_SAI_CR5_W0W

(

x

)

Value:

(((x) - 1) << 16)

REG_SAI_CR5_W0W_MASK

#define REG_SAI_CR5_W0W_MASK   MASK(20, 16)

REG_SAI_CR5_WNW

#define REG_SAI_CR5_WNW

(

x

)

Value:

(((x) - 1) << 24)

REG_SAI_CR5_WNW_MASK

#define REG_SAI_CR5_WNW_MASK   MASK(28, 24)

REG_SAI_CSR_FEF

#define REG_SAI_CSR_FEF   BIT(18)

REG_SAI_CSR_FEIE

#define REG_SAI_CSR_FEIE   BIT(10)

REG_SAI_CSR_FR

#define REG_SAI_CSR_FR   BIT(25)

REG_SAI_CSR_FRDE

#define REG_SAI_CSR_FRDE   BIT(0)

REG_SAI_CSR_FRF

#define REG_SAI_CSR_FRF   BIT(16)

REG_SAI_CSR_FRIE

#define REG_SAI_CSR_FRIE   BIT(8)

REG_SAI_CSR_FWDE

#define REG_SAI_CSR_FWDE   BIT(1)

REG_SAI_CSR_FWF

#define REG_SAI_CSR_FWF   BIT(17)

REG_SAI_CSR_FWIE

#define REG_SAI_CSR_FWIE   BIT(9)

REG_SAI_CSR_SE

#define REG_SAI_CSR_SE   BIT(30)

REG_SAI_CSR_SEF

#define REG_SAI_CSR_SEF   BIT(19)

REG_SAI_CSR_SEIE

#define REG_SAI_CSR_SEIE   BIT(11)

REG_SAI_CSR_SR

#define REG_SAI_CSR_SR   BIT(24)

REG_SAI_CSR_TERE

#define REG_SAI_CSR_TERE   BIT(31)

REG_SAI_CSR_WSF

#define REG_SAI_CSR_WSF   BIT(20)

REG_SAI_CSR_WSIE

#define REG_SAI_CSR_WSIE   BIT(12)

REG_SAI_CSR_XF_MASK

#define REG_SAI_CSR_XF_MASK

Value:

        MASK(REG_SAI_CSR_XF_SHIFT + 4, \
        REG_SAI_CSR_XF_SHIFT)

REG_SAI_CSR_XF_SHIFT

#define REG_SAI_CSR_XF_SHIFT   16

REG_SAI_CSR_XF_W_MASK

#define REG_SAI_CSR_XF_W_MASK

Value:

        MASK(REG_SAI_CSR_XF_W_SHIFT + 2,\
        REG_SAI_CSR_XF_W_SHIFT)

REG_SAI_CSR_XF_W_SHIFT

#define REG_SAI_CSR_XF_W_SHIFT   18

REG_SAI_CSR_XIE_MASK

#define REG_SAI_CSR_XIE_MASK

Value:

        MASK(REG_SAI_CSR_XIE_SHIFT + 4,\
        REG_SAI_CSR_XIE_SHIFT)

REG_SAI_CSR_XIE_SHIFT

#define REG_SAI_CSR_XIE_SHIFT   8

REG_SAI_DMA

#define REG_SAI_DMA   BIT(0)

REG_SAI_FORMATS

#define REG_SAI_FORMATS

Value:

        (SNDRV_PCM_FMTBIT_S16_LE |\
        SNDRV_PCM_FMTBIT_S24_LE |\
        SNDRV_PCM_FMTBIT_S32_LE |\
        SNDRV_PCM_FMTBIT_DSD_U8 |\
        SNDRV_PCM_FMTBIT_DSD_U16_LE |\
        SNDRV_PCM_FMTBIT_DSD_U32_LE)

REG_SAI_MAXBURST_RX

#define REG_SAI_MAXBURST_RX   6

REG_SAI_MAXBURST_TX

#define REG_SAI_MAXBURST_TX   6

REG_SAI_MCLK_MAX

#define REG_SAI_MCLK_MAX   4

REG_SAI_MCTL

#define REG_SAI_MCTL   0x100 /* SAI MCLK Control Register */

REG_SAI_MCTL_DIV_EN

#define REG_SAI_MCTL_DIV_EN   BIT(23)

REG_SAI_MCTL_DIV_MASK

#define REG_SAI_MCTL_DIV_MASK   0xFF

REG_SAI_MCTL_MCLK_EN

#define REG_SAI_MCTL_MCLK_EN   BIT(30) /* MCLK Enable */

REG_SAI_MCTL_MSEL

#define REG_SAI_MCTL_MSEL

(

id

)

Value:

((id) << 24)

REG_SAI_MCTL_MSEL_BUS

#define REG_SAI_MCTL_MSEL_BUS   SET_BITS(25, 24, 0)

REG_SAI_MCTL_MSEL_MASK

#define REG_SAI_MCTL_MSEL_MASK   MASK(25, 24)

REG_SAI_MCTL_MSEL_MCLK1

#define REG_SAI_MCTL_MSEL_MCLK1   SET_BITS(25, 24, 1)

REG_SAI_MCTL_MSEL_MCLK2

#define REG_SAI_MCTL_MSEL_MCLK2   SET_BITS(25, 24, 2)

REG_SAI_MCTL_MSEL_MCLK3

#define REG_SAI_MCTL_MSEL_MCLK3   SET_BITS(25, 24, 3)

REG_SAI_MDIV

#define REG_SAI_MDIV   0x104 /* SAI MCLK Divide Register */

REG_SAI_MDIV_MASK

#define REG_SAI_MDIV_MASK   0xFFFFF

REG_SAI_NET

#define REG_SAI_NET   BIT(2)

REG_SAI_PAR_DLN_MASK

#define REG_SAI_PAR_DLN_MASK   (0x0F)

REG_SAI_PAR_SPF_MASK

#define REG_SAI_PAR_SPF_MASK

Value:

        MASK(REG_SAI_PAR_SPF_SHIFT + 3,\
        REG_SAI_PAR_SPF_SHIFT)

REG_SAI_PAR_SPF_SHIFT

#define REG_SAI_PAR_SPF_SHIFT   16

REG_SAI_PAR_WPF_MASK

#define REG_SAI_PAR_WPF_MASK

Value:

        MASK(REG_SAI_PAR_WPF_SHIFT + 3,\
        REG_SAI_PAR_WPF_SHIFT)

REG_SAI_PAR_WPF_SHIFT

#define REG_SAI_PAR_WPF_SHIFT   8

REG_SAI_PARAM

#define REG_SAI_PARAM   0x04 /* SAI Parameter Register */

REG_SAI_RBCTN

#define REG_SAI_RBCTN   0xf8 /* SAI Receive Bit Counter Register */

REG_SAI_RCR1

#define REG_SAI_RCR1   (0x84 + SAI_OFS) /* SAI Receive Configuration 1 */

REG_SAI_RCR2

#define REG_SAI_RCR2   (0x88 + SAI_OFS) /* SAI Receive Configuration 2 */

REG_SAI_RCR3

#define REG_SAI_RCR3   (0x8c + SAI_OFS) /* SAI Receive Configuration 3 */

REG_SAI_RCR4

#define REG_SAI_RCR4   (0x90 + SAI_OFS) /* SAI Receive Configuration 4 */

REG_SAI_RCR5

#define REG_SAI_RCR5   (0x94 + SAI_OFS) /* SAI Receive Configuration 5 */

REG_SAI_RCSR

#define REG_SAI_RCSR   (0x80 + SAI_OFS) /* SAI Receive Control */

REG_SAI_RDR0

#define REG_SAI_RDR0   0xa0 /* SAI Receive Data */

REG_SAI_RDR1

#define REG_SAI_RDR1   0xa4 /* SAI Receive Data */

REG_SAI_RDR2

#define REG_SAI_RDR2   0xa8 /* SAI Receive Data */

REG_SAI_RDR3

#define REG_SAI_RDR3   0xac /* SAI Receive Data */

REG_SAI_RDR4

#define REG_SAI_RDR4   0xb0 /* SAI Receive Data */

REG_SAI_RDR5

#define REG_SAI_RDR5   0xb4 /* SAI Receive Data */

REG_SAI_RDR6

#define REG_SAI_RDR6   0xb8 /* SAI Receive Data */

REG_SAI_RDR7

#define REG_SAI_RDR7   0xbc /* SAI Receive Data */

REG_SAI_REC_SYN

#define REG_SAI_REC_SYN   BIT(4)

REG_SAI_RFR0

#define REG_SAI_RFR0   0xc0 /* SAI Receive FIFO */

REG_SAI_RFR1

#define REG_SAI_RFR1   0xc4 /* SAI Receive FIFO */

REG_SAI_RFR2

#define REG_SAI_RFR2   0xc8 /* SAI Receive FIFO */

REG_SAI_RFR3

#define REG_SAI_RFR3   0xcc /* SAI Receive FIFO */

REG_SAI_RFR4

#define REG_SAI_RFR4   0xd0 /* SAI Receive FIFO */

REG_SAI_RFR5

#define REG_SAI_RFR5   0xd4 /* SAI Receive FIFO */

REG_SAI_RFR6

#define REG_SAI_RFR6   0xd8 /* SAI Receive FIFO */

REG_SAI_RFR7

#define REG_SAI_RFR7   0xdc /* SAI Receive FIFO */

REG_SAI_RMR

#define REG_SAI_RMR   0xe0 /* SAI Receive Mask */

REG_SAI_RTCAP

#define REG_SAI_RTCAP   0xfc /* SAI Receive Timestamp Capture */

REG_SAI_RTCTL

#define REG_SAI_RTCTL   0xf0 /* SAI Receive Timestamp Control Register */

REG_SAI_RTCTN

#define REG_SAI_RTCTN   0xf4 /* SAI Receive Timestamp Counter Register */

REG_SAI_TBCTN

#define REG_SAI_TBCTN   0x78 /* SAI Transmit Bit Counter Register */

REG_SAI_TCR1

#define REG_SAI_TCR1   (0x04 + SAI_OFS) /* SAI Transmit Configuration 1 */

REG_SAI_TCR2

#define REG_SAI_TCR2   (0x08 + SAI_OFS) /* SAI Transmit Configuration 2 */

REG_SAI_TCR3

#define REG_SAI_TCR3   (0x0c + SAI_OFS) /* SAI Transmit Configuration 3 */

REG_SAI_TCR4

#define REG_SAI_TCR4   (0x10 + SAI_OFS) /* SAI Transmit Configuration 4 */

REG_SAI_TCR5

#define REG_SAI_TCR5   (0x14 + SAI_OFS) /* SAI Transmit Configuration 5 */

REG_SAI_TCSR

#define REG_SAI_TCSR   (0x00 + SAI_OFS) /* SAI Transmit Control */

REG_SAI_TDR0

#define REG_SAI_TDR0   0x20 /* SAI Transmit Data */

REG_SAI_TDR1

#define REG_SAI_TDR1   0x24 /* SAI Transmit Data */

REG_SAI_TDR2

#define REG_SAI_TDR2   0x28 /* SAI Transmit Data */

REG_SAI_TDR3

#define REG_SAI_TDR3   0x2C /* SAI Transmit Data */

REG_SAI_TDR4

#define REG_SAI_TDR4   0x30 /* SAI Transmit Data */

REG_SAI_TDR5

#define REG_SAI_TDR5   0x34 /* SAI Transmit Data */

REG_SAI_TDR6

#define REG_SAI_TDR6   0x38 /* SAI Transmit Data */

REG_SAI_TDR7

#define REG_SAI_TDR7   0x3C /* SAI Transmit Data */

REG_SAI_TFR0

#define REG_SAI_TFR0   0x40 /* SAI Transmit FIFO */

REG_SAI_TFR1

#define REG_SAI_TFR1   0x44 /* SAI Transmit FIFO */

REG_SAI_TFR2

#define REG_SAI_TFR2   0x48 /* SAI Transmit FIFO */

REG_SAI_TFR3

#define REG_SAI_TFR3   0x4C /* SAI Transmit FIFO */

REG_SAI_TFR4

#define REG_SAI_TFR4   0x50 /* SAI Transmit FIFO */

REG_SAI_TFR5

#define REG_SAI_TFR5   0x54 /* SAI Transmit FIFO */

REG_SAI_TFR6

#define REG_SAI_TFR6   0x58 /* SAI Transmit FIFO */

REG_SAI_TFR7

#define REG_SAI_TFR7   0x5C /* SAI Transmit FIFO */

REG_SAI_TMR

#define REG_SAI_TMR   0x60 /* SAI Transmit Mask */

REG_SAI_TRA_SYN

#define REG_SAI_TRA_SYN   BIT(3)

REG_SAI_TTCAP

#define REG_SAI_TTCAP   0x7C /* SAI Transmit Timestamp Capture */

REG_SAI_TTCTL

#define REG_SAI_TTCTL   0x70 /* SAI Transmit Timestamp Control Register */

REG_SAI_TTCTN

#define REG_SAI_TTCTN   0x74 /* SAI Transmit Timestamp Counter Register */

REG_SAI_USE_AC97

#define REG_SAI_USE_AC97   BIT(1)

REG_SAI_USE_I2S_SLAVE

#define REG_SAI_USE_I2S_SLAVE   BIT(5)

REG_SAI_VER_EFIFO_EN

#define REG_SAI_VER_EFIFO_EN   BIT(0)

REG_SAI_VER_ID_MASK

#define REG_SAI_VER_ID_MASK

Value:

        MASK(REG_SAI_VER_ID_SHIFT + 15,\
        REG_SAI_VER_ID_SHIFT)

REG_SAI_VER_ID_SHIFT

#define REG_SAI_VER_ID_SHIFT   16

REG_SAI_VER_TSTMP_EN

#define REG_SAI_VER_TSTMP_EN   BIT(1)

REG_SAI_VERID

#define REG_SAI_VERID   0x00 /* SAI Version ID Register */

REG_SAI_XCR1

#define REG_SAI_XCR1

(

rx

)

Value:

(rx ? REG_SAI_RCR1 : REG_SAI_TCR1)

REG_SAI_XCR2

#define REG_SAI_XCR2

(

rx

)

Value:

(rx ? REG_SAI_RCR2 : REG_SAI_TCR2)

REG_SAI_XCR3

#define REG_SAI_XCR3

(

rx

)

Value:

(rx ? REG_SAI_RCR3 : REG_SAI_TCR3)

REG_SAI_XCR4

#define REG_SAI_XCR4

(

rx

)

Value:

(rx ? REG_SAI_RCR4 : REG_SAI_TCR4)

REG_SAI_XCR5

#define REG_SAI_XCR5

(

rx

)

Value:

(rx ? REG_SAI_RCR5 : REG_SAI_TCR5)

REG_SAI_XCSR

#define REG_SAI_XCSR

(

rx

)

Value:

(rx ? REG_SAI_RCSR : REG_SAI_TCSR)

REG_SAI_XMR

#define REG_SAI_XMR

(

rx

)

Value:

(rx ? REG_SAI_RMR  : REG_SAI_TMR)

REG_SAI_XMR_MASK

#define REG_SAI_XMR_MASK   0xffffffff

SAI_FIFO_WORD_SIZE

#define SAI_FIFO_WORD_SIZE   64

SAI_FLAG_PMQOS

#define SAI_FLAG_PMQOS   BIT(0)

SAI_OFS

#define SAI_OFS   0

Variable Documentation

sai_driver

const struct dai_driver sai_driver

extern