sdma.h File Reference

Go to the source code of this file.

Macros
#define	SDMA_MC0PTR   0x0000 /* platform 0 control block */
#define	SDMA_INTR   0x0004 /* Active interrupts, W1C */
#define	SDMA_STOP_STAT   0x0008 /* Channel stop/status, W1C */
#define	SDMA_HSTART   0x000C /* Channel start */
#define	SDMA_EVTOVR   0x0010 /* Event override */
#define	SDMA_DSPOVR   0x0014 /* Channel BP override */
#define	SDMA_HOSTOVR   0x0018 /* ARM platform override */
#define	SDMA_EVTPEND   0x001C /* Pending events */
#define	SDMA_RESET   0x0024 /* Reset register */
#define	SDMA_EVTERR   0x0028 /* DMA request error */
#define	SDMA_INTRMASK   0x002C /* ARM platform interrupt mask */
#define	SDMA_PSW   0x0030 /* Schedule status */
#define	SDMA_EVTERRDBG   0x0034 /* DMA request error register */
#define	SDMA_CONFIG   0x0038 /* Configuration register */
#define	SDMA_CONFIG_ACR   BIT(4)
#define	SDMA_CONFIG_CSM_MSK   MASK(1, 0)
#define	SDMA_CONFIG_CSM_STATIC   SET_BITS(1, 0, 0) /* Static ctx switch */
#define	SDMA_CONFIG_CSM_DYN_LP   SET_BITS(1, 0, 1) /* Low power; unused */
#define	SDMA_CONFIG_CSM_DYN_NL   SET_BITS(1, 0, 2) /* No loops; unused */
#define	SDMA_CONFIG_CSM_DYN   SET_BITS(1, 0, 3) /* Fully dynamic ctx switch */
#define	SDMA_LOCK   0x003C /* Lock firmware until reset */
#define	SDMA_ONCE_ENB   0x0040 /* Enable OnCE */
#define	SDMA_ONCE_DATA   0x0044 /* OnCE data register */
#define	SDMA_ONCE_INSTR   0x0048 /* OnCE instruction register */
#define	SDMA_ONCE_STAT   0x004C /* OnCE status register */
#define	SDMA_ONCE_CMD   0x0050 /* OnCE command register */
#define	SDMA_ILLINSTADDR   0x0058
#define	SDMA_CHN0ADDR   0x005C /* Channel 0 boot address */
#define	SDMA_EVT_MIRROR   0x0060 /* DMA requests */
#define	SDMA_EVT_MIRROR2   0x0064 /* DMA requests */
#define	SDMA_XTRIG_CONF1   0x0070
#define	SDMA_XTRIG_CONF2   0x0074
#define	SDMA_CHNPRI(chan)
#define	SDMA_DEFPRI   4
#define	SDMA_MAXPRI   7
#define	SDMA_HWEVENTS_COUNT   48
#define	SDMA_CHNENBL(hwchan)
#define	SDMA_DONE0_CONFIG   0x1000
#define	SDMA_DONE1_CONFIG   0x1004
#define	SDMA_DONE0_CONFIG_DONE_SEL   BIT(7)
#define	SDMA_DONE0_CONFIG_DONE_DIS   BIT(6)
#define	SDMA_WATERMARK_LEVEL_N_FIFOS(x)
#define	SDMA_WATERMARK_LEVEL_OFF_FIFOS(x)
#define	SDMA_WATERMARK_LEVEL_WORDS_PER_FIFO(x)
#define	SDMA_WATERMARK_LEVEL_SW_DONE   BIT(23)
#define	SDMA_WATERMARK_LEVEL_SW_DONE_SEL_OFF   24
#define	SDMA_BD_COUNT_MASK   MASK(15, 0)
#define	SDMA_BD_COUNT(n)
#define	SDMA_BD_MAX_COUNT   SDMA_BD_COUNT_MASK
#define	SDMA_BD_DONE   BIT(16)
#define	SDMA_BD_WRAP   BIT(17)
#define	SDMA_BD_CONT   BIT(18)
#define	SDMA_BD_INT   BIT(19)
#define	SDMA_BD_ERROR   BIT(20)
#define	SDMA_BD_LAST   BIT(21)
#define	SDMA_BD_EXTD   BIT(23)
#define	SDMA_BD_CMD_MASK   MASK(31, 24)
#define	SDMA_BD_CMD(cmd)
#define	SDMA_MAX_BDS   4
#define	SDMA_CMD_C0_SET_PM   0x4
#define	SDMA_CMD_C0_SET_DM   0x1
#define	SDMA_CMD_C0_GET_PM   0x8
#define	SDMA_CMD_C0_GET_DM   0x2
#define	SDMA_CMD_C0_SETCTX(chan)
#define	SDMA_CMD_C0_GETCTX(chan)
#define	SDMA_CMD_XFER_SIZE(s)
#define	SDMA_SRAM_CONTEXTS_BASE   0x800
#define	SDMA_CHAN_TYPE_AP2AP   0
#define	SDMA_CHAN_TYPE_AP2MCU   1
#define	SDMA_CHAN_TYPE_MCU2AP   2
#define	SDMA_CHAN_TYPE_SHP2MCU   3
#define	SDMA_CHAN_TYPE_MCU2SHP   4
#define	SDMA_CHAN_TYPE_SAI2MCU   5
#define	SDMA_SCRIPT_AP2AP_OFF   644
#define	SDMA_SCRIPT_AP2MCU_OFF   685
#define	SDMA_SCRIPT_MCU2AP_OFF   749
#define	SDMA_SCRIPT_SHP2MCU_OFF   893
#define	SDMA_SCRIPT_MCU2SHP_OFF   962
#define	SDMA_SCRIPT_SAI2MCU_OFF   6710

Macro Definition Documentation

SDMA_BD_CMD

#define SDMA_BD_CMD

(

cmd

)

Value:

SET_BITS(31, 24, cmd)

SDMA_BD_CMD_MASK

#define SDMA_BD_CMD_MASK   MASK(31, 24)

SDMA_BD_CONT

#define SDMA_BD_CONT   BIT(18)

SDMA_BD_COUNT

#define SDMA_BD_COUNT

(

n

)

Value:

SET_BITS(15, 0, n)

SDMA_BD_COUNT_MASK

#define SDMA_BD_COUNT_MASK   MASK(15, 0)

SDMA_BD_DONE

#define SDMA_BD_DONE   BIT(16)

SDMA_BD_ERROR

#define SDMA_BD_ERROR   BIT(20)

SDMA_BD_EXTD

#define SDMA_BD_EXTD   BIT(23)

SDMA_BD_INT

#define SDMA_BD_INT   BIT(19)

SDMA_BD_LAST

#define SDMA_BD_LAST   BIT(21)

SDMA_BD_MAX_COUNT

#define SDMA_BD_MAX_COUNT   SDMA_BD_COUNT_MASK

SDMA_BD_WRAP

#define SDMA_BD_WRAP   BIT(17)

SDMA_CHAN_TYPE_AP2AP

#define SDMA_CHAN_TYPE_AP2AP   0

SDMA_CHAN_TYPE_AP2MCU

#define SDMA_CHAN_TYPE_AP2MCU   1

SDMA_CHAN_TYPE_MCU2AP

#define SDMA_CHAN_TYPE_MCU2AP   2

SDMA_CHAN_TYPE_MCU2SHP

#define SDMA_CHAN_TYPE_MCU2SHP   4

SDMA_CHAN_TYPE_SAI2MCU

#define SDMA_CHAN_TYPE_SAI2MCU   5

SDMA_CHAN_TYPE_SHP2MCU

#define SDMA_CHAN_TYPE_SHP2MCU   3

SDMA_CHN0ADDR

#define SDMA_CHN0ADDR   0x005C /* Channel 0 boot address */

SDMA_CHNENBL

#define SDMA_CHNENBL

(

hwchan

)

Value:

(0x0200 + 4 * (hwchan))

SDMA_CHNPRI

#define SDMA_CHNPRI

(

chan

)

Value:

(0x0100 + 4 * (chan))

SDMA_CMD_C0_GET_DM

#define SDMA_CMD_C0_GET_DM   0x2

SDMA_CMD_C0_GET_PM

#define SDMA_CMD_C0_GET_PM   0x8

SDMA_CMD_C0_GETCTX

#define SDMA_CMD_C0_GETCTX

(

chan

)

Value:

(((chan) << 3) | 6)

SDMA_CMD_C0_SET_DM

#define SDMA_CMD_C0_SET_DM   0x1

SDMA_CMD_C0_SET_PM

#define SDMA_CMD_C0_SET_PM   0x4

SDMA_CMD_C0_SETCTX

#define SDMA_CMD_C0_SETCTX

(

chan

)

Value:

(((chan) << 3) | 7)

SDMA_CMD_XFER_SIZE

#define SDMA_CMD_XFER_SIZE

(

s

)

Value:

((s) == 8 ? 1 : (s) == 16 ? 2 : (s) == 24 ? 3 : 0)

SDMA_CONFIG

#define SDMA_CONFIG   0x0038 /* Configuration register */

SDMA_CONFIG_ACR

#define SDMA_CONFIG_ACR   BIT(4)

SDMA_CONFIG_CSM_DYN

#define SDMA_CONFIG_CSM_DYN   SET_BITS(1, 0, 3) /* Fully dynamic ctx switch */

SDMA_CONFIG_CSM_DYN_LP

#define SDMA_CONFIG_CSM_DYN_LP   SET_BITS(1, 0, 1) /* Low power; unused */

SDMA_CONFIG_CSM_DYN_NL

#define SDMA_CONFIG_CSM_DYN_NL   SET_BITS(1, 0, 2) /* No loops; unused */

SDMA_CONFIG_CSM_MSK

#define SDMA_CONFIG_CSM_MSK   MASK(1, 0)

SDMA_CONFIG_CSM_STATIC

#define SDMA_CONFIG_CSM_STATIC   SET_BITS(1, 0, 0) /* Static ctx switch */

SDMA_DEFPRI

#define SDMA_DEFPRI   4

SDMA_DONE0_CONFIG

#define SDMA_DONE0_CONFIG   0x1000

SDMA_DONE0_CONFIG_DONE_DIS

#define SDMA_DONE0_CONFIG_DONE_DIS   BIT(6)

SDMA_DONE0_CONFIG_DONE_SEL

#define SDMA_DONE0_CONFIG_DONE_SEL   BIT(7)

SDMA_DONE1_CONFIG

#define SDMA_DONE1_CONFIG   0x1004

SDMA_DSPOVR

#define SDMA_DSPOVR   0x0014 /* Channel BP override */

SDMA_EVT_MIRROR

#define SDMA_EVT_MIRROR   0x0060 /* DMA requests */

SDMA_EVT_MIRROR2

#define SDMA_EVT_MIRROR2   0x0064 /* DMA requests */

SDMA_EVTERR

#define SDMA_EVTERR   0x0028 /* DMA request error */

SDMA_EVTERRDBG

#define SDMA_EVTERRDBG   0x0034 /* DMA request error register */

SDMA_EVTOVR

#define SDMA_EVTOVR   0x0010 /* Event override */

SDMA_EVTPEND

#define SDMA_EVTPEND   0x001C /* Pending events */

SDMA_HOSTOVR

#define SDMA_HOSTOVR   0x0018 /* ARM platform override */

SDMA_HSTART

#define SDMA_HSTART   0x000C /* Channel start */

SDMA_HWEVENTS_COUNT

#define SDMA_HWEVENTS_COUNT   48

SDMA_ILLINSTADDR

#define SDMA_ILLINSTADDR   0x0058

SDMA_INTR

#define SDMA_INTR   0x0004 /* Active interrupts, W1C */

SDMA_INTRMASK

#define SDMA_INTRMASK   0x002C /* ARM platform interrupt mask */

SDMA_LOCK

#define SDMA_LOCK   0x003C /* Lock firmware until reset */

SDMA_MAX_BDS

#define SDMA_MAX_BDS   4

SDMA_MAXPRI

#define SDMA_MAXPRI   7

SDMA_MC0PTR

#define SDMA_MC0PTR   0x0000 /* platform 0 control block */

SDMA_ONCE_CMD

#define SDMA_ONCE_CMD   0x0050 /* OnCE command register */

SDMA_ONCE_DATA

#define SDMA_ONCE_DATA   0x0044 /* OnCE data register */

SDMA_ONCE_ENB

#define SDMA_ONCE_ENB   0x0040 /* Enable OnCE */

SDMA_ONCE_INSTR

#define SDMA_ONCE_INSTR   0x0048 /* OnCE instruction register */

SDMA_ONCE_STAT

#define SDMA_ONCE_STAT   0x004C /* OnCE status register */

SDMA_PSW

#define SDMA_PSW   0x0030 /* Schedule status */

SDMA_RESET

#define SDMA_RESET   0x0024 /* Reset register */

SDMA_SCRIPT_AP2AP_OFF

#define SDMA_SCRIPT_AP2AP_OFF   644

SDMA_SCRIPT_AP2MCU_OFF

#define SDMA_SCRIPT_AP2MCU_OFF   685

SDMA_SCRIPT_MCU2AP_OFF

#define SDMA_SCRIPT_MCU2AP_OFF   749

SDMA_SCRIPT_MCU2SHP_OFF

#define SDMA_SCRIPT_MCU2SHP_OFF   962

SDMA_SCRIPT_SAI2MCU_OFF

#define SDMA_SCRIPT_SAI2MCU_OFF   6710

SDMA_SCRIPT_SHP2MCU_OFF

#define SDMA_SCRIPT_SHP2MCU_OFF   893

SDMA_SRAM_CONTEXTS_BASE

#define SDMA_SRAM_CONTEXTS_BASE   0x800

SDMA_STOP_STAT

#define SDMA_STOP_STAT   0x0008 /* Channel stop/status, W1C */

SDMA_WATERMARK_LEVEL_N_FIFOS

#define SDMA_WATERMARK_LEVEL_N_FIFOS

(

x

)

Value:

SET_BITS(15, 12, x)

SDMA_WATERMARK_LEVEL_OFF_FIFOS

#define SDMA_WATERMARK_LEVEL_OFF_FIFOS

(

x

)

Value:

SET_BITS(19, 16, x)

SDMA_WATERMARK_LEVEL_SW_DONE

#define SDMA_WATERMARK_LEVEL_SW_DONE   BIT(23)

SDMA_WATERMARK_LEVEL_SW_DONE_SEL_OFF

#define SDMA_WATERMARK_LEVEL_SW_DONE_SEL_OFF   24

SDMA_WATERMARK_LEVEL_WORDS_PER_FIFO

#define SDMA_WATERMARK_LEVEL_WORDS_PER_FIFO

(

x

)

Value:

SET_BITS(31, 28, x)

SDMA_XTRIG_CONF1

#define SDMA_XTRIG_CONF1   0x0070

SDMA_XTRIG_CONF2

#define SDMA_XTRIG_CONF2   0x0074