fw_reg.h

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/* SPDX-License-Identifier: BSD-3-Clause
 *
 * Copyright(c) 2021 Intel Corporation. All rights reserved.
 */
 
/*
 * This file contains structures that are exact copies of an existing ABI used
 * by IOT middleware. They are Intel specific and will be used by one middleware.
 *
 * Some of the structures may contain programming implementations that makes them
 * unsuitable for generic use and general usage.
 *
 * This code is mostly copied "as-is" from existing C++ interface files hence the use of
 * different style in places. The intention is to keep the interface as close as possible to
 * original so it's easier to track changes with IPC host code.
 */
 
#ifndef __IPC4_FW_REG_H__
#define __IPC4_FW_REG_H__
 
#include <stdint.h>
#include <ipc4/error_status.h>
#include <ipc4/module.h>
#include <sof/lib/cpu.h>
 
struct ipc4_fw_status_reg {
    uint32_t state      : 28; 
    uint32_t module     : 3;  
    uint32_t running    : 1;  
} __attribute__((packed, aligned(4)));
 
typedef uint32_t ipc4_last_error;
 
struct ipc4_fw_pwr_status {
    uint32_t curr_astate : 4;             
    uint32_t cached_imr_usage_status  : 1; 
    uint32_t curr_fstate : 3;             
    uint32_t wake_tick_period : 5;        
    uint32_t active_pipelines_count : 6;  
    uint32_t rsvd0 : 13;                  
} __attribute__((packed, aligned(4)));
 
struct ipc4_pipeline_registers {
    uint64_t stream_start_offset;
    uint64_t stream_end_offset;
} __attribute__((packed, aligned(8)));
 
#define IPC4_PV_MAX_SUPPORTED_CHANNELS 8
 
struct ipc4_peak_volume_regs {
    uint32_t peak_meter[IPC4_PV_MAX_SUPPORTED_CHANNELS];     
    uint32_t current_volume[IPC4_PV_MAX_SUPPORTED_CHANNELS]; 
    uint32_t target_volume[IPC4_PV_MAX_SUPPORTED_CHANNELS];  
} __attribute__((packed, aligned(4)));
 
struct ipc4_llp_reading {
    uint32_t llp_l;  
    uint32_t llp_u;  
    uint32_t wclk_l; 
    uint32_t wclk_u; 
} __attribute__((packed, aligned(4)));
 
struct ipc4_llp_reading_extended {
    struct ipc4_llp_reading llp_reading; 
    uint32_t tpd_low;                    
    uint32_t tpd_high;                   
} __attribute__((packed, aligned(4)));
 
struct ipc4_llp_reading_slot {
    uint32_t node_id;                 
    struct ipc4_llp_reading reading;  
} __attribute__((packed, aligned(4)));
 
union ipc4_rom_info {
    struct {
        uint32_t fuse_values: 8;                 
        uint32_t load_method: 1;                 
        uint32_t downlink_IPC_use_DMA: 1;        
        uint32_t load_method_reserved: 2;        
        uint32_t implementation_revision_min: 4; 
        uint32_t implementation_revision_maj: 4; 
        uint32_t implementation_version_min: 4;  
        uint32_t implementation_version_maj: 4;  
        uint32_t reserved : 4;                   
    } bits; 
    struct {
        uint32_t rsvd1: 16; 
        uint32_t type: 12;  
        uint32_t rsvd2: 4;  
    } platform; 
} __attribute__((packed, aligned(4)));
 
#define IPC4_MAX_SUPPORTED_ADSP_CORES 8
 
#define IPC4_MAX_PIPELINE_REG_SLOTS 16
 
#define IPC4_MAX_PEAK_VOL_REG_SLOTS 16
 
#define IPC4_MAX_LLP_GPDMA_READING_SLOTS 24
 
#define IPC4_MAX_LLP_SNDW_READING_SLOTS 16
 
#define IPC4_FW_REGS_ABI_VER 1
 
struct ipc4_fw_registers {
    struct ipc4_fw_status_reg fsr; 
    ipc4_last_error lec;           
    struct ipc4_fw_pwr_status fps; 
    uint32_t lnec;                 
    uint32_t ltr;                  
    uint32_t rsvd0;                
    union ipc4_rom_info rom_info;  
    uint32_t abi_ver;              
    uint8_t slave_core_sts[IPC4_MAX_SUPPORTED_ADSP_CORES]; 
    uint32_t rsvd2[6];             
    struct ipc4_pipeline_registers pipeline_regs[IPC4_MAX_PIPELINE_REG_SLOTS]; 
    struct ipc4_peak_volume_regs peak_vol_regs[IPC4_MAX_PEAK_VOL_REG_SLOTS];   
    struct ipc4_llp_reading_slot llp_gpdma_reading_slots[IPC4_MAX_LLP_GPDMA_READING_SLOTS]; 
    struct ipc4_llp_reading_slot llp_sndw_reading_slots[IPC4_MAX_LLP_SNDW_READING_SLOTS - 1]; 
    struct ipc4_llp_reading_slot llp_evad_reading_slot; 
} __attribute__((packed, aligned(4)));
 
#endif