ipc4_fw_pwr_status Struct Reference

Firmware power and clock status register (offset 0x8 in Mailbox Window 0). More...

#include <src/include/ipc4/fw_reg.h>

Data Fields
uint32_t	curr_astate: 4
	Currently active A-state index.
uint32_t	cached_imr_usage_status: 1
	Cached IMR usage status from previous D0i3.
uint32_t	curr_fstate: 3
	Currently active F-state index.
uint32_t	wake_tick_period: 5
	Wake tick period configuration.
uint32_t	active_pipelines_count: 6
	Number of currently active pipelines.
uint32_t	rsvd0: 13
	Reserved padding bits.

Detailed Description

Firmware power and clock status register (offset 0x8 in Mailbox Window 0).

Field Documentation

active_pipelines_count

uint32_t ipc4_fw_pwr_status::active_pipelines_count

Number of currently active pipelines.

cached_imr_usage_status

uint32_t ipc4_fw_pwr_status::cached_imr_usage_status

Cached IMR usage status from previous D0i3.

curr_astate

uint32_t ipc4_fw_pwr_status::curr_astate

Currently active A-state index.

curr_fstate

uint32_t ipc4_fw_pwr_status::curr_fstate

Currently active F-state index.

rsvd0

uint32_t ipc4_fw_pwr_status::rsvd0

Reserved padding bits.

wake_tick_period

uint32_t ipc4_fw_pwr_status::wake_tick_period

Wake tick period configuration.

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The documentation for this struct was generated from the following file:

• src/include/ipc4/fw_reg.h