Sample Rate Conversion Architecture (SRC & ASRC)#
The Sample Rate Conversion subsystem in Sound Open Firmware provides real-time sampling frequency transformations across heterogeneous audio streams, mixing buses, and hardware peripherals.
Modern audio platforms must seamlessly interconnect disparate sample rates: 44.1 kHz (compact discs, MP3, AAC), 48 kHz (standard pro-audio, video, Bluetooth SBC/mSBC), 16 kHz (speech recognition, voice wake-word engines), and 96/192 kHz (high-resolution DACs). Furthermore, when interfacing with independent external hardware clocks (such as USB Audio Class, Bluetooth LE Audio, HDMI/DisplayPort PLLs, or external codecs), clock frequencies drift over time, requiring continuous fractional compensation.
SOF addresses these challenges through two specialized architectural components:
Synchronous Sample Rate Converter (SRC) (
src/audio/src/): Converts sample rates by exact, mathematically locked rational ratios (\(M / N\)) using a multi-stage polyphase FIR filter bank.Asynchronous Sample Rate Converter (ASRC) (
src/audio/asrc/): Converts sample rates across independent, unsynchronized clock domains using a polynomial Farrow filter structure coupled with a closed-loop drift tracking controller.
This guide provides a comprehensive, high-level architectural walkthrough of the SRC and ASRC subsystems, polyphase filter banks, Farrow polynomial structures, push/pull modes, and SIMD hardware acceleration without delving into low-level C code.
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1. Sample Rate Conversion in Audio Systems#
Audio systems process signals sampled at discrete time intervals. When two connected components operate at different sampling frequencies, digital sample rate conversion is required to change the effective time interval between samples without introducing audible acoustic distortion, aliasing, or spectral imaging.
Synchronous vs Asynchronous Taxonomy#
The fundamental distinction between SRC and ASRC lies in whether the input and output sampling clocks share a locked timebase:
Synchronous Sample Rate Conversion (SRC):
Input rate \(F_{\text{in}}\) and output rate \(F_{\text{out}}\) are derived from the same physical clock tree or share an exact, immutable rational ratio \(M / N\).
For every \(N\) input frames consumed, exactly \(M\) output frames are produced.
Ideal for intra-DSP conversions (e.g. upsampling a 44.1 kHz MP3 stream to the 48 kHz pipeline mixing bus, or downsampling 48 kHz microphone audio to 16 kHz for a voice keyword recognizer).
Asynchronous Sample Rate Conversion (ASRC):
Input and output sampling clocks originate from independent physical crystal oscillators (e.g. a host PC USB clock vs an embedded DSP oscillator, or an external S/PDIF transceiver vs an internal audio PLL).
Due to physical manufacturing tolerances and thermal fluctuations, crystals exhibit drift (typically 20 to 100 parts per million). Over seconds or minutes, clock drift causes cumulative sample count discrepancies that lead to buffer underrun or overrun.
ASRC continuously tracks clock drift and applies time-varying fractional interpolation, maintaining a constant buffer watermark without audible pitch distortion or clicks.
Figure 63 Architectural Taxonomy: Synchronous SRC (Fixed M/N Ratio) vs Asynchronous ASRC (Drifting Clocks)#
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2. Synchronous SRC: Polyphase Filter Bank Architecture#
In classic digital signal processing textbooks, sample rate conversion by a rational fraction \(M / N\) is described as a three-step sequence: upsampling by \(M\) (inserting \(M-1\) zero-valued samples), low-pass filtering to eliminate spectral imaging, and downsampling by \(N\) (retaining every \(N\)-th sample).
The Inefficiency of Textbook Interpolation#
Implementing textbook zero-stuffing directly in DSP firmware would be disastrously inefficient:
For a conversion from 44.1 kHz to 48 kHz (\(M/N = 160/147\)), upsampling by 160 requires inserting 159 zeros between every sample, inflating the intermediate sample rate to \(44.1 \times 160 = 7.056\text{ MHz}\).
Over 99% of multiply-accumulate operations in the FIR filter would multiply filter coefficients by zero, wasting immense processor power.
The Polyphase Filter Bank Optimization#
Sound Open Firmware implements the Polyphase Filter Bank decomposition. In a polyphase architecture:
Subfilter Decomposition: The large prototype low-pass FIR filter is mathematically partitioned into \(M\) smaller subfilters (phases), where subfilter \(p\) contains coefficients \(h[kM + p]\).
Zero Elimination: Because the locations of non-zero input samples are known deterministically, zero-valued samples are never inserted or computed.
Lowest-Rate Filtering: Filtering operations execute directly at the input sample rate. For each output sample required, the engine selects the appropriate polyphase subfilter branch and computes a short dot-product against historical input samples stored in a circular delay line.
Figure 64 Polyphase Filter Bank Interpolation and Decimation Mechanics in Synchronous SRC#
Quality and Memory Footprint Profiles#
SOF allows system integrators to configure filter complexity via compile-time Kconfig settings:
Standard Profile (``COMP_SRC_STD``): Studio-grade conversion quality. Exceeds 120 dB signal-to-noise ratio (SNR) with stopband rejection greater than 100 dB and passband ripple below 0.001 dB, ideal for high-fidelity 24-bit/32-bit music playback.
Small Profile (``COMP_SRC_SMALL``): Balanced profile offering ~100 dB SNR while halving filter coefficient memory tables.
Tiny / Lite Profiles (``COMP_SRC_TINY`` / ``COMP_SRC_LITE``): Ultra-compact filter sets tailored for memory-constrained microcontrollers and speech streams (e.g. 16 kHz to 48 kHz).
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3. Multi-Stage Conversion & Latency Optimization#
Converting between sample rates in the same family (e.g. 48 kHz to 96 kHz, ratio \(2/1\), or 32 kHz to 48 kHz, ratio \(3/2\)) requires low-order filters and introduces minimal latency.
However, cross-family conversions (such as 44.1 kHz to 48 kHz) present severe mathematical challenges. The exact ratio is:
The Latency Penalty of Single-Stage Conversion#
In a single-stage converter:
The numerator \(M = 160\) and denominator \(N = 147\) require processing blocks of 147 input samples producing 160 output samples.
At 44.1 kHz, 147 samples corresponds to 3.33 ms of algorithmic latency, and steep anti-aliasing filter requirements inflate the total delay line buffer requirement to over 13.3 ms.
For real-time communications, gaming, and interactive audio, 13 ms of added latency is unacceptable.
The Two-Stage Factored Pipeline Solution#
SOF resolves this by factoring difficult conversion fractions into two cascaded stages:
Figure 65 Multi-Stage Conversion Pipeline (e.g. 44.1 kHz to 48 kHz Factored into 2 Stages with Halfband Filters)#
Benefits of Two-Stage Conversion#
Shorter Buffer Latency: Granularity drops from 147 frames to 21 frames, reducing buffer latency by more than 75%.
Computational Efficiency: Halfband filters possess symmetric impulse responses where nearly 50% of the coefficients are exactly zero, eliminating half of the required multiplication operations.
Reduced Memory Footprint: Total filter coefficient storage and delay line allocations are dramatically lower than a monolithic 160/147 single-stage filter.
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4. Asynchronous ASRC: Farrow Filter Structure#
When audio traverses independent clock domains—such as streaming over Bluetooth (where the remote earbud clock is slightly slower than the phone’s clock) or recording from a USB microphone—the ratio between input and output sample rates is not a fixed rational number. Instead, the ratio drifts continuously over time:
The Failure of Conventional Polyphase Filters for Drift#
A polyphase filter bank requires precomputed coefficient tables for a specific, fixed rational fraction \(M / N\). If the clock drifts by even 15 parts per million, the true conversion fraction changes into an irrational or unmanageably large ratio, making static polyphase tables useless.
The Farrow Polynomial Structure#
The Asynchronous Sample Rate Converter (implemented in src/audio/asrc/asrc_farrow.c) uses the Farrow structure. Invented by Cecil W. Farrow, this architecture evaluates continuous fractional delay filtering:
Polynomial Approximation: The impulse response \(h(t)\) of the continuous interpolation filter is approximated by a set of \(P\)-th order polynomials over each sample interval:
\[h(t) \approx \sum_{k=0}^{P} c_k(n) \cdot \mu^k\]where \(\mu \in [0, 1)\) represents the fractional sample delay (the exact sub-sample time offset where the output sample lies between two input samples).
Parallel Fixed Subfilters: The filter coefficients \(c_k(n)\) are fixed and precomputed at compile time. The input audio signal is passed through \(P+1\) parallel fixed FIR filter branches.
Continuous Polynomial Interpolation: The outputs of the parallel branches are multiplied by successive powers of \(\mu\) using Horner’s rule:
\[y(t) = C_0 + \mu \cdot \left( C_1 + \mu \cdot \left( C_2 + \mu \cdot C_3 \right) \right)\]
Figure 66 Asynchronous Farrow Filter Structure with Continuous Fractional Delay Parameter µ#
Because \(\mu\) is a continuous floating-point or high-precision fixed-point value, the Farrow structure can synthesize output samples at any arbitrary sub-sample time point on the fly, requiring zero table updates or DSP filter recalculations.
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5. Closed-Loop Drift Estimation & Buffer Watermark Control#
While the Farrow structure provides the mathematical capability to interpolate at any arbitrary time offset \(\mu\), the ASRC requires an intelligent control system to determine what \(\mu\) should be at every moment in time.
The Closed-Loop Feedback Architecture#
The ASRC subsystem implements a closed-loop Drift Estimator and watermark tracking controller:
Watermark Monitoring: The controller continuously tracks the fill level (number of available frames) in the secondary buffer.
Phase Error Calculation: If the output clock is running faster than nominal, the secondary buffer level gradually falls below the target watermark. If the output clock is running slower, the buffer level rises.
Fractional Step Adjustment: The drift estimator calculates the exact clock phase error \(\Delta \mu\) and updates the step increment:
\[\mu_{n+1} = (\mu_n + \Delta t) \pmod 1.0\]Zero-Crossing Compensation: By continuously nudging \(\Delta t\), the controller maintains a stable, steady-state buffer watermark, preventing buffer starvation and buffer overflow indefinitely.
Figure 67 Closed-Loop Drift Estimation & Buffer Watermark Control in ASRC#
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6. Push-Mode vs Pull-Mode Operational Topologies#
Because rate conversion alters the relationship between consumed and produced frames, an ASRC component cannot simultaneously satisfy fixed-size buffer constraints on both its input and output pins.
To accommodate different audio streaming directions, the ASRC provides two operational modes:
Push-Mode Operation (Playback / Transmit)#
Operation: The caller feeds a fixed number of input frames into the ASRC on each period (e.g. 48 frames).
Production: Depending on the instantaneous clock drift and fractional ratio, the ASRC produces a variable number of output frames (e.g. 47, 48, or 49 frames).
Topology: Used in playback pipelines where the DSP pushes audio toward an external digital audio interface (such as a Bluetooth controller or external DAC) that dictates the downstream clock. The output is coupled to a circular ring buffer to absorb production variance.
Pull-Mode Operation (Capture / Receive)#
Operation: The downstream consumer requests a fixed number of output frames on each period.
Consumption: The ASRC pulls a variable number of input frames from its input ring buffer to synthesize the requested output block.
Topology: Used in capture pipelines where an external peripheral (e.g. a USB microphone or S/PDIF receiver) produces samples at its own hardware clock, and the DSP pulls audio into a synchronous processing graph.
Figure 68 Push-Mode vs Pull-Mode Execution Topologies across Audio Interfaces#
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7. SIMD Vector Acceleration Across DSP Architectures#
Both polyphase FIR filtering (in SRC) and polynomial Farrow evaluation (in ASRC) are computationally intensive, requiring dozens of multiply-accumulate operations per sample across multi-channel streams.
SOF provides highly optimized vector assembly implementations tailored for Tensilica Xtensa DSP architectures:
Cadence Tensilica Xtensa HiFi 3 (``src_hifi3.c``, ``asrc_farrow_hifi3.c``):
Utilizes 64-bit dual multiply-accumulate instructions (
AE_MULAA32RA,AE_S32X2).Processes two 32-bit channels or samples in parallel with hardware saturation.
Cadence Tensilica Xtensa HiFi 4 (``src_hifi4.c``):
Employs 128-bit SIMD registers (
ae_int32x4) executing four 32x32 multiplications per clock cycle.Leverages circular buffer address pointers (
AE_L32X4_XC) to advance delay line pointers without scalar address math.
Cadence Tensilica Xtensa HiFi 5 (``src_hifi5.c``, ``asrc_farrow_hifi5.c``):
8-way vector processing engine executing eight 32-bit multiply-accumulate operations concurrently.
Dual 128-bit memory load buses ensure that filter coefficients and audio delay lines are fetched with zero cache wait states.
Generic Portable C Reference (``src_generic.c``, ``asrc_farrow_generic.c``):
Clean, portable scalar C implementations designed for non-Xtensa platforms (e.g. ARM Cortex-M7 on Teensy 4.1, RISC-V on ESP32-P4).
Figure 69 SIMD Vector Processing & Circular Delay Line Buffering across Hardware Architectures#
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