TGL Memory

8000 0000h

Aliasing to A000 0000h - BFFF FFFFh range (non L1 cacheable).

A000 0000h

L2 cacheable memory (L1 cacheable).

B000 0000h

L2 uncacheable memory (L1 cacheable). IMR (4MB size), see IMR Allocation.

BE00 0000h

L2 local HPSRAM (L1 cacheable). Seen as 8MB of virtual memory space (46 * 64KB).


By default, address virtualization is disabled. The Translation Lookup Buffer (TLB) entries for populated HPSRAM banks have the same values for virtual addresses and physical addresses.

BE80 0000h

L2 local LPSRAM (L1 cacheable). Accessed using physical addresses (1 * 64KB).

9F00 0000h

L1 local D-SRAM (512 KB) Directly accessed from core #0 only.

9F10 0000h

L1 local I-SRAM (512 KB) Directly accessed from core #0 only.


The SOF version that will add Local L1 Data & Instruction SRAM support is subject to future development.

9F18 0000h

DSP ROM Code Directly accessed from core #0 only.

digraph G { node [fontsize=10, shape="record"] edge [fontsize=10] rankdir=LR splines=line dsp [label="DSP"] mem_rom [label="<rom>ROM\n9F18 00000\n(512KB)"] mem_alias [label="<a>Alias\n8000 0000\n" group="memory"] mem [label="<imr> IMR\nB000 0000 |<hpsram> HPSRAM\nBE00 0000 |<lpsram> LPSRAM\nBE80 0000 |<l1dsram> L1DSRAM\n9F10 000 |<l1isram> L1ISRAM\n9F18 0000" group="memory"] dsp -> mem_alias:a [label="L1 uncached"] dsp -> mem:imr [label="L1 cached"] dsp -> mem:hpsram [label="L1 cached"] dsp -> mem:lpsram [label="L1 cached"] dsp -> mem:l1dsram [label="L1 local"] dsp -> mem:l1isram [label="L1 local"] }

Figure 14 TGL Memory Map